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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [blockMemory/] [simulation/] [functional/] [simulate_mti.do] - Blame information for rev 5

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# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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#
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# Xilinx, and to the maximum extent permitted by applicable
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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#--------------------------------------------------------------------------------
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 vlib work
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vmap work work
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echo "Compiling Core VHDL UNISIM/Behavioral model"
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vcom  -work work ../../../blockMemory.vhd \
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    ../../example_design/blockMemory_exdes.vhd
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echo "Compiling Test Bench Files"
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vcom -work work    ../bmg_tb_pkg.vhd
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vcom -work work    ../random.vhd
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vcom -work work    ../data_gen.vhd
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vcom -work work    ../addr_gen.vhd
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vcom -work work    ../checker.vhd
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vcom -work work    ../bmg_stim_gen.vhd
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vcom -work work    ../blockMemory_synth.vhd
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vcom -work work    ../blockMemory_tb.vhd
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vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb
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#Disabled waveform to save the disk space
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add log -r /*
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#Ignore integer warnings at time 0
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set StdArithNoWarnings 1
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run 0
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set StdArithNoWarnings 0
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run -all

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