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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [blockMemory/] [simulation/] [timing/] [simulate_isim.bat] - Blame information for rev 5

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:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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::
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::--------------------------------------------------------------------------------
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echo "Compiling Core VHDL UNISIM/Behavioral model"
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vhpcomp  -work work ..\..\implement\results\routed.vhd
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echo "Compiling Test Bench Files"
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vhpcomp -work work    ..\bmg_tb_pkg.vhd
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vhpcomp -work work    ..\random.vhd
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vhpcomp -work work    ..\data_gen.vhd
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vhpcomp -work work    ..\addr_gen.vhd
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vhpcomp -work work    ..\checker.vhd
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vhpcomp -work work    ..\bmg_stim_gen.vhd
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vhpcomp -work work    ..\blockMemory_synth.vhd
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vhpcomp -work work    ..\blockMemory_tb.vhd
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    fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe
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.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl

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