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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [blockMemory/] [simulation/] [timing/] [simulate_vcs.sh] - Blame information for rev 5

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# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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#--------------------------------------------------------------------------------
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#!/bin/sh
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rm -rf simv* csrc DVEfiles AN.DB
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echo "Compiling Core VHDL UNISIM/Behavioral model"
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vhdlan  ../../implement/results/routed.vhd
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echo "Compiling Test Bench Files"
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vhdlan    ../bmg_tb_pkg.vhd
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vhdlan    ../random.vhd
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vhdlan    ../data_gen.vhd
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vhdlan    ../addr_gen.vhd
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vhdlan    ../checker.vhd
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vhdlan    ../bmg_stim_gen.vhd
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vhdlan    ../blockMemory_synth.vhd
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vhdlan    ../blockMemory_tb.vhd
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echo "Elaborating Design"
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vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb
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echo "Simulating Design"
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./simv -ucli -i ucli_commands.key
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dve -session vcs_session.tcl

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