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                Core name: Xilinx LogiCORE Block Memory Generator
                Version: 7.1
                Release: ISE 14.1 / Vivado 2012.1
                Release Date: April 24, 2012
 
 
================================================================================
 
This document contains the following sections:
 
This document contains the following sections:
 
1. Introduction
2. New Features
  2.1 ISE
  2.2 Vivado
3. Supported Devices
  3.1 ISE
  3.2 Vivado
4. Resolved Issues
  4.1 ISE
  4.2 Vivado
5. Known Issues
  5.1 ISE
  5.2 Vivado
6. Technical Support
7. Core Release History
8. Legal Disclaimer
 
================================================================================
 
 
1. INTRODUCTION
 
For installation instructions for this release, please go to:
 
  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
 
For system requirements:
 
   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
 
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1
solution. For the latest core updates, see the product page at:
 
 <A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
 
 
................................................................................
2. NEW FEATURES
 
 
  2.1 ISE
 
    - ISE 14.1 software support
    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
      and Automotive Zynq device support
 
 
  2.2 Vivado
 
    - 2012.1 software support
    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
      and Automotive Zynq device support
 
 
................................................................................
3. SUPPORTED DEVICES
 
 
  3.1 ISE
 
  The following device families are supported by the core for this release.
 
  All 7 Series devices
  Zynq-7000 devices
  All Virtex-6 devices
  All Spartan-6 devices
  All Virtex-5 devices
  All Spartan-3 devices
  All Virtex-4 devices
 
 
  3.2 Vivado
  All 7 Series devices
  Zynq-7000 devices
 
 
................................................................................
4. RESOLVED ISSUES
 
 
The following issues are resolved in Block Memory Generator v7.1:
 
  4.1 ISE
 
 
  4.2 Vivado
 
 
................................................................................
5. KNOWN ISSUES
 
 
  5.1 ISE
 
    The following are known issues for v7.1 of this core at time of release:
 
    1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
      Work around: The user must review the possible scenarios that causes the collission and revise
       their design to avoid those situations.
      - CR588505
 
      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
            Write Mode = Read First in conjunction with asynchronous clocking
 
    2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
 
    3. Core does not generate for large memories. Depending on the
       machine the ISE CORE Generator software runs on, the maximum size of the memory that
       can be generated will vary.  For example, a Dual Pentium-4 server
       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
      - CR 415768
      - AR 24034
 
 
  5.2 Vivado
 
  The most recent information, including known issues, workarounds, and resolutions for
  this version is provided in the IP Release Notes User Guide located at
 
         <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
 
 
 
................................................................................
6. TECHNICAL SUPPORT
 
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
 
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
 
 
 
7. CORE RELEASE HISTORY
 
Date        By            Version      Description
================================================================================
04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue
12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
                                       Device support; Automotive Spartan 3A
                                       DSP device support
09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
07/2007     Xilinx, Inc.  2.5          Revised to v2.5
04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
02/2007     Xilinx, Inc.  2.4          Revised to v2.4
11/2006     Xilinx, Inc.  2.3          Revised to v2.3
09/2006     Xilinx, Inc.  2.2          Revised to v2.2
06/2006     Xilinx, Inc.  2.1          Revised to v2.1
01/2006     Xilinx, Inc.  1.1          Initial release
================================================================================
 
8. Legal Disclaimer
 
 (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.
 
 This file contains confidential and proprietary information
 of Xilinx, Inc. and is protected under U.S. and
 international copyright and other intellectual property
 laws.
 
 DISCLAIMER
 This disclaimer is not a license and does not grant any
 rights to the materials distributed herewith. Except as
 otherwise provided in a valid license issued to you by
 Xilinx, and to the maximum extent permitted by applicable
 law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 (2) Xilinx shall not be liable (whether in contract or tort,
 including negligence, or under any other theory of
 liability) for any loss or damage of any kind or nature
 related to, arising under or in connection with these
 materials, including for any direct, or any indirect,
 special, incidental, or consequential loss or damage
 (including loss of data, profits, goodwill, or any type of
 loss or damage suffered as a result of any action brought
 by a third party) even if such damage or loss was
 reasonably foreseeable or Xilinx had been advised of the
 possibility of the same.
 
 CRITICAL APPLICATIONS
 Xilinx products are not designed or intended to be fail-
 safe, or for use in any application requiring fail-safe
 performance, such as life-support or safety devices or
 systems, Class III medical devices, nuclear facilities,
 applications related to the deployment of airbags, or any
 other applications that could lead to death, personal
 injury, or severe property or environmental damage
 (individually and collectively, "Critical
 Applications"). Customer assumes the sole risk and
 liability of any use of Xilinx products in Critical
 Applications, subject only to applicable laws and
 regulations governing limitations on product liability.
 
 THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 PART OF THIS FILE AT ALL TIMES.
 
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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory/] [doc/] [blk_mem_gen_v7_1_vinfo.html] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	gajos	`<HTML>`
2			`<HEAD>`
3			`<TITLE>blk_mem_gen_v7_1_vinfo</TITLE>`
4			`<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">`
5			`</HEAD>`
6			`<BODY>`
7			`<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">`
8			`Core name: Xilinx LogiCORE Block Memory Generator`
9			`Version: 7.1`
10			`Release: ISE 14.1 / Vivado 2012.1`
11			`Release Date: April 24, 2012`
12
13
14			`================================================================================`
15
16			`This document contains the following sections:`
17
18			`This document contains the following sections:`
19
20			`1. Introduction`
21			`2. New Features`
22			`2.1 ISE`
23			`2.2 Vivado`
24			`3. Supported Devices`
25			`3.1 ISE`
26			`3.2 Vivado`
27			`4. Resolved Issues`
28			`4.1 ISE`
29			`4.2 Vivado`
30			`5. Known Issues`
31			`5.1 ISE`
32			`5.2 Vivado`
33			`6. Technical Support`
34			`7. Core Release History`
35			`8. Legal Disclaimer`
36
37			`================================================================================`
38
39
40			`1. INTRODUCTION`
41
42			`For installation instructions for this release, please go to:`
43
44			`<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>`
45
46			`For system requirements:`
47
48			`<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>`
49
50			`This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1`
51			`solution. For the latest core updates, see the product page at:`
52
53			`<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>`
54
55
56			`................................................................................`
57			`2. NEW FEATURES`
58
59
60			`2.1 ISE`
61
62			`- ISE 14.1 software support`
63			`- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,`
64			`and Automotive Zynq device support`
65
66
67			`2.2 Vivado`
68
69			`- 2012.1 software support`
70			`- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,`
71			`and Automotive Zynq device support`
72
73
74			`................................................................................`
75			`3. SUPPORTED DEVICES`
76
77
78			`3.1 ISE`
79
80			`The following device families are supported by the core for this release.`
81
82			`All 7 Series devices`
83			`Zynq-7000 devices`
84			`All Virtex-6 devices`
85			`All Spartan-6 devices`
86			`All Virtex-5 devices`
87			`All Spartan-3 devices`
88			`All Virtex-4 devices`
89
90
91			`3.2 Vivado`
92			`All 7 Series devices`
93			`Zynq-7000 devices`
94
95
96			`................................................................................`
97			`4. RESOLVED ISSUES`
98
99
100			`The following issues are resolved in Block Memory Generator v7.1:`
101
102			`4.1 ISE`
103
104
105			`4.2 Vivado`
106
107
108			`................................................................................`
109			`5. KNOWN ISSUES`
110
111
112			`5.1 ISE`
113
114			`The following are known issues for v7.1 of this core at time of release:`
115
116			`1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)`
117			`Work around: The user must review the possible scenarios that causes the collission and revise`
118			`their design to avoid those situations.`
119			`- CR588505`
120
121			`Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with`
122			`Write Mode = Read First in conjunction with asynchronous clocking`
123
124			`2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.`
125
126			`3. Core does not generate for large memories. Depending on the`
127			`machine the ISE CORE Generator software runs on, the maximum size of the memory that`
128			`can be generated will vary. For example, a Dual Pentium-4 server`
129			`with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes`
130			`- CR 415768`
131			`- AR 24034`
132
133
134			`5.2 Vivado`
135
136			`The most recent information, including known issues, workarounds, and resolutions for`
137			`this version is provided in the IP Release Notes User Guide located at`
138
139			`<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>`
140
141
142
143			`................................................................................`
144			`6. TECHNICAL SUPPORT`
145
146			`To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>`
147			`Questions are routed to a team with expertise using this product.`
148
149			`Xilinx provides technical support for use of this product when used`
150			`according to the guidelines described in the core documentation, and`
151			`cannot guarantee timing, functionality, or support of this product for`
152			`designs that do not follow specified guidelines.`
153
154
155
156			`7. CORE RELEASE HISTORY`
157
158			`Date By Version Description`
159			`================================================================================`
160			`04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support`
161			`01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L, AArtix-7 device support`
162			`06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;`
163			`03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support`
164			`09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support`
165			`07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support`
166			`04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support`
167			`03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue`
168			`12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power`
169			`Device support; Automotive Spartan 3A`
170			`DSP device support`
171			`09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3`
172			`06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2`
173			`04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1`
174			`09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8`
175			`03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7`
176			`10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6`
177			`07/2007 Xilinx, Inc. 2.5 Revised to v2.5`
178			`04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1`
179			`02/2007 Xilinx, Inc. 2.4 Revised to v2.4`
180			`11/2006 Xilinx, Inc. 2.3 Revised to v2.3`
181			`09/2006 Xilinx, Inc. 2.2 Revised to v2.2`
182			`06/2006 Xilinx, Inc. 2.1 Revised to v2.1`
183			`01/2006 Xilinx, Inc. 1.1 Initial release`
184			`================================================================================`
185
186			`8. Legal Disclaimer`
187
188			`(c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.`
189
190			`This file contains confidential and proprietary information`
191			`of Xilinx, Inc. and is protected under U.S. and`
192			`international copyright and other intellectual property`
193			`laws.`
194
195			`DISCLAIMER`
196			`This disclaimer is not a license and does not grant any`
197			`rights to the materials distributed herewith. Except as`
198			`otherwise provided in a valid license issued to you by`
199			`Xilinx, and to the maximum extent permitted by applicable`
200			`law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
201			`WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
202			`AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
203			`BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
204			`INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
205			`(2) Xilinx shall not be liable (whether in contract or tort,`
206			`including negligence, or under any other theory of`
207			`liability) for any loss or damage of any kind or nature`
208			`related to, arising under or in connection with these`
209			`materials, including for any direct, or any indirect,`
210			`special, incidental, or consequential loss or damage`
211			`(including loss of data, profits, goodwill, or any type of`
212			`loss or damage suffered as a result of any action brought`
213			`by a third party) even if such damage or loss was`
214			`reasonably foreseeable or Xilinx had been advised of the`
215			`possibility of the same.`
216
217			`CRITICAL APPLICATIONS`
218			`Xilinx products are not designed or intended to be fail-`
219			`safe, or for use in any application requiring fail-safe`
220			`performance, such as life-support or safety devices or`
221			`systems, Class III medical devices, nuclear facilities,`
222			`applications related to the deployment of airbags, or any`
223			`other applications that could lead to death, personal`
224			`injury, or severe property or environmental damage`
225			`(individually and collectively, "Critical`
226			`Applications"). Customer assumes the sole risk and`
227			`liability of any use of Xilinx products in Critical`
228			`Applications, subject only to applicable laws and`
229			`regulations governing limitations on product liability.`
230
231			`THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
232			`PART OF THIS FILE AT ALL TIMES.`
233
234			`</FONT>`
235			`</PRE>`
236			`</BODY>`
237			`</HTML>`