Subversion Repositories mod_mult_exp

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--

-- BLK MEM GEN v7_1 Core - Data Generator

--

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--

-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.

--

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--

-- Filename: data_gen.vhd

--

-- Description:

--   Data Generator

--

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-- Author: IP Solutions Division

--

-- History: Sep 12, 2011 - First Release

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--

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-- Library Declarations

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY work;

USE work.BMG_TB_PKG.ALL;

ENTITY DATA_GEN IS

  GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;

            DOUT_WIDTH     : INTEGER := 32;

            DATA_PART_CNT  : INTEGER := 1;

            SEED           : INTEGER := 2

  );

  PORT (

        CLK      : IN STD_LOGIC;

        RST      : IN STD_LOGIC;

        EN       : IN STD_LOGIC;

        DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           

  );

END DATA_GEN;

ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS

  CONSTANT LOOP_COUNT     : INTEGER   := DIVROUNDUP(DATA_GEN_WIDTH,8);

  SIGNAL   RAND_DATA      : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);

  SIGNAL   LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);

  SIGNAL   LOCAL_CNT      : INTEGER   :=1;

  SIGNAL   DATA_GEN_I     : STD_LOGIC :='0';

BEGIN

  LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);

  DATA_OUT       <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));

  DATA_GEN_I     <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;

  PROCESS(CLK)

  BEGIN

     IF(RISING_EDGE (CLK)) THEN

        IF(EN ='1' AND (DATA_PART_CNT =1)) THEN

           LOCAL_CNT <=1;

        ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN

           IF(LOCAL_CNT = 1) THEN

              LOCAL_CNT <= LOCAL_CNT+1;

           ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN

              LOCAL_CNT <= LOCAL_CNT+1;

           ELSE

              LOCAL_CNT <= 1;

           END IF;

        ELSE

          LOCAL_CNT <= 1;

        END IF;

     END IF;

  END PROCESS;

  RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE

    RAND_GEN_INST:ENTITY work.RANDOM

       GENERIC MAP(

           WIDTH => 8,

           SEED => (SEED+N)

       )

       PORT MAP(

          CLK => CLK,

              RST => RST,

          EN  => DATA_GEN_I,

          RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)

       );

  END GENERATE RAND_GEN;

END ARCHITECTURE;