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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory.vho] - Blame information for rev 5

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--    This file is owned and controlled by Xilinx and must be used solely     --
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--    for design, simulation, implementation and creation of design files     --
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--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
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--    devices or technologies is expressly prohibited and immediately         --
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--    terminates your license.                                                --
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--                                                                            --
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--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
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--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
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--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
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--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
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--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
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--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
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--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
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--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
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--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
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--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
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--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
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--    PARTICULAR PURPOSE.                                                     --
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--                                                                            --
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--    Xilinx products are not intended for use in life support appliances,    --
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--    devices, or systems.  Use in such applications are expressly            --
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--    prohibited.                                                             --
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--                                                                            --
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--    (c) Copyright 1995-2015 Xilinx, Inc.                                    --
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--    All rights reserved.                                                    --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--    Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1      --
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--                                                                            --
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--    The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port    --
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--    Block Memory and Single Port Block Memory LogiCOREs, but is not a       --
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--    direct drop-in replacement.  It should be used in all new Xilinx        --
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--    designs. The core supports RAM and ROM functions over a wide range of   --
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--    widths and depths. Use this core to generate block memories with        --
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--    symmetric or asymmetric read and write port widths, as well as cores    --
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--    which can perform simultaneous write operations to separate             --
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--    locations, and simultaneous read operations from the same location.     --
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--    For more information on differences in interface and feature support    --
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--    between this core and the Dual Port Block Memory and Single Port        --
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--    Block Memory LogiCOREs, please consult the data sheet.                  --
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--------------------------------------------------------------------------------
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-- Interfaces:
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--    AXI_SLAVE_S_AXI
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--        AXI_SLAVE
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--    AXILite_SLAVE_S_AXI
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--        AXILite_SLAVE
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--    BRAM_PORTA
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--        BRAM_PORTA
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--    BRAM_PORTB
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--        BRAM_PORTB
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-- The following code must appear in the VHDL architecture header:
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT blockMemory
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  PORT (
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    clka : IN STD_LOGIC;
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    rsta : IN STD_LOGIC;
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    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
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  );
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : blockMemory
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  PORT MAP (
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    clka => clka,
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    rsta => rsta,
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    wea => wea,
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    addra => addra,
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    dina => dina,
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    douta => douta
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  );
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-- INST_TAG_END ------ End INSTANTIATION Template ------------
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-- You must compile the wrapper file blockMemory.vhd when simulating
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-- the core, blockMemory. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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