OpenCores
URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

Subversion Repositories mod_mult_exp

[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory.xco] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 gajos
##############################################################
2
#
3
# Xilinx Core Generator version 14.2
4
# Date: Sun Feb 01 11:01:19 2015
5
#
6
##############################################################
7
#
8
#  This file contains the customisation parameters for a
9
#  Xilinx CORE Generator IP GUI. It is strongly recommended
10
#  that you do not manually alter this file as it may cause
11
#  unexpected and unsupported behavior.
12
#
13
##############################################################
14
#
15
#  Generated from component: xilinx.com:ip:blk_mem_gen:7.1
16
#
17
##############################################################
18
#
19
# BEGIN Project Options
20
SET addpads = false
21
SET asysymbol = true
22
SET busformat = BusFormatAngleBracketNotRipped
23
SET createndf = false
24
SET designentry = VHDL
25
SET device = xc3s500e
26
SET devicefamily = spartan3e
27
SET flowvendor = Other
28
SET formalverification = false
29
SET foundationsym = false
30
SET implementationfiletype = Ngc
31
SET package = fg320
32
SET removerpms = false
33
SET simulationfiles = Behavioral
34
SET speedgrade = -5
35
SET verilogsim = false
36
SET vhdlsim = true
37
# END Project Options
38
# BEGIN Select
39
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.1
40
# END Select
41
# BEGIN Parameters
42
CSET additional_inputs_for_power_estimation=false
43
CSET algorithm=Fixed_Primitives
44
CSET assume_synchronous_clk=false
45
CSET axi_id_width=4
46
CSET axi_slave_type=Memory_Slave
47
CSET axi_type=AXI4_Full
48
CSET byte_size=9
49
CSET coe_file=no_coe_file_loaded
50
CSET collision_warnings=ALL
51
CSET component_name=blockMemory
52
CSET disable_collision_warnings=false
53
CSET disable_out_of_range_warnings=false
54
CSET ecc=false
55
CSET ecctype=No_ECC
56
CSET enable_32bit_address=false
57
CSET enable_a=Always_Enabled
58
CSET enable_b=Always_Enabled
59
CSET error_injection_type=Single_Bit_Error_Injection
60
CSET fill_remaining_memory_locations=false
61
CSET interface_type=Native
62
CSET load_init_file=false
63
CSET memory_type=Single_Port_RAM
64
CSET operating_mode_a=READ_FIRST
65
CSET operating_mode_b=WRITE_FIRST
66
CSET output_reset_value_a=0
67
CSET output_reset_value_b=0
68
CSET pipeline_stages=0
69
CSET port_a_clock=100
70
CSET port_a_enable_rate=100
71
CSET port_a_write_rate=50
72
CSET port_b_clock=100
73
CSET port_b_enable_rate=100
74
CSET port_b_write_rate=50
75
CSET primitive=256x72
76
CSET read_width_a=64
77
CSET read_width_b=64
78
CSET register_porta_input_of_softecc=false
79
CSET register_porta_output_of_memory_core=false
80
CSET register_porta_output_of_memory_primitives=false
81
CSET register_portb_output_of_memory_core=false
82
CSET register_portb_output_of_memory_primitives=false
83
CSET register_portb_output_of_softecc=false
84
CSET remaining_memory_locations=0
85
CSET reset_memory_latch_a=false
86
CSET reset_memory_latch_b=false
87
CSET reset_priority_a=CE
88
CSET reset_priority_b=CE
89
CSET reset_type=SYNC
90
CSET softecc=false
91
CSET use_axi_id=false
92
CSET use_byte_write_enable=false
93
CSET use_error_injection_pins=false
94
CSET use_regcea_pin=false
95
CSET use_regceb_pin=false
96
CSET use_rsta_pin=true
97
CSET use_rstb_pin=false
98
CSET write_depth_a=16
99
CSET write_width_a=64
100
CSET write_width_b=64
101
# END Parameters
102
# BEGIN Extra information
103
MISC pkg_timestamp=2012-05-01T17:17:26Z
104
# END Extra information
105
GENERATE
106
# CRC: b6414ecb

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.