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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory_beh.cgp] - Blame information for rev 5

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Line No. Rev Author Line
1 5 gajos
# Date: Sat Dec 22 01:24:09 2012
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc3s500e
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SET devicefamily = spartan3e
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fg320
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -5
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SET verilogsim = false
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SET vhdlsim = true
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SET workingdirectory = .\tmp\
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# CRC: 46f7aa00

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