Subversion Repositories mod_mult_exp

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"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns FALSE.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns FALSE.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Range is empty (null range)

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Assignment ignored

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Range is empty (null range)

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Assignment ignored

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Range is empty (null range)

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Assignment ignored

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 370: Net <doutb_i[71]> does not have a driver.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[71]> does not have a driver.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[71]> does not have a driver.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns FALSE.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <doutb> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal.

Input <S_AXI_AWID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WDATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000).

Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000).

Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WEA<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WEB<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.

"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.

Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal 'dina_pad<71>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<62>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<53>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<44>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<71>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<62>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<53>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<44>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000).

Input <DOUTB_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RDADDRECC_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

You have chosen to run a version of XST which is not the default solution

for the specified device family. You are free to use it in order to take

advantage of its enhanced HDL parsing/elaboration capabilities. However,

please be aware that you may be impacted by  language support differences.

This version may also result in circuit performance and device utilization

differences for your particular design. You can always revert back to the

default XST solution by setting the "use_new_parser" option to value "no"

on the XST command line or in the XST process properties panel.