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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_mult/] [ModMultIter_SM.vhd] - Blame information for rev 3

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1 3 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Montgomery modular multiplier and exponentiator               ----
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----                                                               ----
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---- This file is part of the Montgomery modular multiplier        ----
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---- and exponentiator project                                     ----
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---- http://opencores.org/project,mod_mult_exp                     ----
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----                                                               ----
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---- Description:                                                  ----
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----   This is state machine for the modular multiplier it consists----
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----   of three states, NOP the preparation stage, CALCULATE_START ----
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----   for the modular multiply and STOP for the presentation      ----
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----   result.                                                     ----
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----                                                               ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2014 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.properties.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ModMultIter_SM is
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    generic (
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             word_size : integer := WORD_LENGTH;
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             word_binary : integer := WORD_INTEGER
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         );
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    port(
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        x             : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);
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                  start         : in  STD_LOGIC;
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                  clk           : in  STD_LOGIC;
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                  s_0           : in  STD_LOGIC;
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                  y_0           : in  STD_LOGIC;
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                  ready         : out STD_LOGIC;
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                  out_reg_en    : out STD_LOGIC;
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                  mux_mult_ctrl : out STD_LOGIC;
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                  mux_4in_ctrl  : out STD_LOGIC_VECTOR(1 downto 0)
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         );
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end ModMultIter_SM;
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architecture Behavioral of ModMultIter_SM is
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signal state            : multiplier_states := NOP;
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signal next_state       : multiplier_states := NOP;
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signal position_counter : STD_LOGIC_VECTOR(word_binary downto 0) := (others => '0');
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signal shift_reg        : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0');
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signal q : STD_LOGIC;
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begin
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    q <= (shift_reg(0) and y_0) xor s_0;
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    mux_4in_ctrl <= shift_reg(0) & q;
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         SM : process(state, start, position_counter)
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             begin
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                                case state is
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                                    -- Prepare for the Montgomery iterations
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                                    when NOP =>
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                                             ready <= '0';
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                                             if (start = '1') then
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                                                                next_state <= CALCULATE_START;
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                                                                out_reg_en <= '1';
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                                  mux_mult_ctrl <= '1';
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                                                  else
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                                                      out_reg_en <= '0';
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                                  mux_mult_ctrl <= '0';
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                                                                next_state <= NOP;
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                                                  end if;
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                                         -- State for the calculations of the Montgomery iterations
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                                         when CALCULATE_START =>
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                                                      mux_mult_ctrl <= '1';
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                                                                ready <= '0';
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                                                          -- End of iterations (counter contains the 'word_size' number)
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                                                      if (position_counter = (word_size - 1)) then
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                                                                    out_reg_en <= '0';
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                                                                         next_state <= STOP;
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                                                           -- Calculation process
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                                                           else
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                                                                    out_reg_en <= '1';
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                                                                    next_state <= CALCULATE_START;
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                                                                end if;
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                                         -- End of the calculations
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                                         when STOP =>
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                                             ready <= '1';
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                                             mux_mult_ctrl <= '1';
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                                                  out_reg_en <= '0';
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                                             if (start = '1') then
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                                                                next_state <= STOP;
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                                                  else
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                                                      next_state <= NOP;
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                                                  end if;
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                           end case;
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                  end process SM;
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        -- Shift register enabling proper calculations of the all Montgomery iterations
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    shift : process (clk, state)
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         begin
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             if (clk = '0' and clk'Event) then
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                           if (state = CALCULATE_START) then
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                                         shift_reg <= shift_reg(0) & shift_reg(word_size - 1 downto 1);
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                           else
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                                         shift_reg <= x;
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                           end if;
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                  end if;
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         end process shift;
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        -- Process for the state change between each clock tick
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    state_control : process (clk, start)
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        begin
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            if (start = '0') then
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                    state <= NOP;
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                                         elsif (clk = '1' and clk'Event) then
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                    state <= next_state;
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            end if;
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        end process state_control;
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    -- Counter for controlling the number of the montgomery iterations during counting
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    couner_modifier : process (clk)
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             begin
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                      if (clk = '1' and clk'Event) then
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                                        if (state = CALCULATE_START) then
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                                                 position_counter <= position_counter + 1;
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                                        else
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                                                 position_counter <= (others => '0');
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                                        end if;
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                                end if;
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                  end process couner_modifier;
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end Behavioral;

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