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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [axi_tb.vhd] - Blame information for rev 84

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1 84 JonasDC
----------------------------------------------------------------------  
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----  axi_tb                                                      ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    testbench for the AXI-Lite interface, functions are       ----
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----    provided to read and write data                           ----
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----    writes bus transfers to out/axi_output                    ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - mod_sim_exp_core                                        ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library std;
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use std.textio.all;
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library ieee;
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use ieee.std_logic_textio.all;
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entity axi_tb is
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end axi_tb;
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architecture arch of axi_tb is
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  -- constants
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  constant CLK_PERIOD : time := 10 ns;
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  constant C_S_AXI_DATA_WIDTH : integer := 32;
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  constant C_S_AXI_ADDR_WIDTH : integer := 32;
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  file output : text open write_mode is "out/axi_output.txt";
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  ------------------------------------------------------------------
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  -- Core parameters
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  ------------------------------------------------------------------
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  constant C_NR_BITS_TOTAL   : integer := 1536;
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  constant C_NR_STAGES_TOTAL : integer := 96;
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  constant C_NR_STAGES_LOW   : integer := 32;
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  constant C_SPLIT_PIPELINE  : boolean := true;
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  constant C_FIFO_DEPTH      : integer := 32; -- set to (maximum exponent width)/16
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  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
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  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
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  constant C_BASEADDR        : std_logic_vector(0 to 31) := x"A0000000";
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  constant C_HIGHADDR        : std_logic_vector(0 to 31) := x"A0007FFF";
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80
  -------------------------
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  -- AXI4lite interface
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  -------------------------
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  --- Global signals
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  signal S_AXI_ACLK    : std_logic;
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  signal S_AXI_ARESETN : std_logic;
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  --- Write address channel
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  signal S_AXI_AWADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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  signal S_AXI_AWVALID : std_logic;
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  signal S_AXI_AWREADY : std_logic;
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  --- Write data channel
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  signal S_AXI_WDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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  signal S_AXI_WVALID : std_logic;
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  signal S_AXI_WREADY : std_logic;
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  signal S_AXI_WSTRB  : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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  --- Write response channel
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  signal S_AXI_BVALID : std_logic;
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  signal S_AXI_BREADY : std_logic;
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  signal S_AXI_BRESP  : std_logic_vector(1 downto 0);
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  --- Read address channel
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  signal S_AXI_ARADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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  signal S_AXI_ARVALID : std_logic;
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  signal S_AXI_ARREADY : std_logic;
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  --- Read data channel
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  signal S_AXI_RDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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  signal S_AXI_RVALID : std_logic;
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  signal S_AXI_RREADY : std_logic;
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  signal S_AXI_RRESP  : std_logic_vector(1 downto 0);
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109
begin
110
 
111
  ------------------------------------------
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  -- Generate clk
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  ------------------------------------------
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  clk_process : process
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  begin
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    while (true) loop
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      S_AXI_ACLK <= '0';
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      wait for CLK_PERIOD/2;
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      S_AXI_ACLK <= '1';
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      wait for CLK_PERIOD/2;
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    end loop;
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  end process;
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124
 
125
  stim_proc : process
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127
    variable Lw : line;
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129
    procedure waitclk(n : natural := 1) is
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    begin
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      for i in 1 to n loop
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        wait until rising_edge(S_AXI_ACLK);
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      end loop;
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    end waitclk;
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136
    procedure axi_write( address : std_logic_vector(31 downto 0);
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                         data    : std_logic_vector(31 downto 0) ) is
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      variable counter : integer := 0;
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    begin
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      -- place address on the bus
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      wait until rising_edge(S_AXI_ACLK);
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      S_AXI_AWADDR <= address;
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      S_AXI_AWVALID <= '1';
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      S_AXI_WDATA <= data;
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      S_AXI_WVALID <= '1';
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      S_AXI_WSTRB <= "1111";
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      while (counter /= 2) loop -- wait for slave response
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        wait until rising_edge(S_AXI_ACLK);
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        if (S_AXI_AWREADY='1') then
150
          S_AXI_AWVALID <= '0';
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          counter := counter+1;
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        end if;
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        if (S_AXI_WREADY='1') then
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          S_AXI_WVALID <= '0';
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          counter := counter+1;
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        end if;
157
      end loop;
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      S_AXI_BREADY <= '1';
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      if S_AXI_BVALID/='1' then
160
        wait until S_AXI_BVALID='1';
161
      end if;
162
 
163
      write(Lw, string'("Wrote "));
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      hwrite(Lw, data);
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      write(Lw, string'(" to   "));
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      hwrite(Lw, address);
167
 
168
      if (S_AXI_BRESP /= "00") then
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        write(Lw, string'("   --> Error! Status: "));
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        write(Lw, S_AXI_BRESP);
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      end if;
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      writeline(output, Lw);
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      wait until rising_edge(S_AXI_ACLK);
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      S_AXI_BREADY <= '0';
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    end axi_write;
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    procedure axi_read( address  : std_logic_vector(31 downto 0) ) is
179
    begin
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      -- place address on the bus
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      wait until rising_edge(S_AXI_ACLK);
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      S_AXI_ARADDR <= address;
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      S_AXI_ARVALID <= '1';
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      wait until S_AXI_ARREADY='1';
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      wait until rising_edge(S_AXI_ACLK);
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      S_AXI_ARVALID <= '0';
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      -- wait for read data
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      S_AXI_RREADY <= '1';
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      wait until S_AXI_RVALID='1';
190
      wait until rising_edge(S_AXI_ACLK);
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      write(Lw, string'("Read  "));
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      hwrite(Lw, S_AXI_RDATA);
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      write(Lw, string'(" from "));
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      hwrite(Lw, address);
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      if (S_AXI_RRESP /= "00") then
198
        write(Lw, string'("   --> Error! Status: "));
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        write(Lw, S_AXI_RRESP);
200
      end if;
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      writeline(output, Lw);
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      S_AXI_RREADY <= '0';
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      --assert false report "Wrote " & " to " & " Status=" & to_string(S_AXI_BRESP) severity note;
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    end axi_read;
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208
  begin
209
 
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    write(Lw, string'("----------------------------------------------"));
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    writeline(output, Lw);
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    write(Lw, string'("--            AXI BUS SIMULATION            --"));
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    writeline(output, Lw);
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    write(Lw, string'("----------------------------------------------"));
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    writeline(output, Lw);
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    S_AXI_AWADDR <= (others=>'0');
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    S_AXI_AWVALID <= '0';
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    S_AXI_WDATA <= (others=>'0');
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    S_AXI_WVALID <= '0';
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    S_AXI_WSTRB <= (others=>'0');
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    S_AXI_BREADY <= '0';
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    S_AXI_ARADDR <= (others=>'0');
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    S_AXI_ARVALID <= '0';
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    S_AXI_RREADY <= '0';
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226
    S_AXI_ARESETN <= '0';
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    waitclk(10);
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    S_AXI_ARESETN <= '1';
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    waitclk(20);
230
 
231
    axi_write(x"A0000000", x"11111111");
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    axi_read(x"A0000000");
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    axi_write(x"A0001000", x"01234567");
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    axi_read(x"A0001000");
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    axi_write(x"A0002000", x"AAAAAAAA");
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    axi_read(x"A0002000");
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    axi_write(x"A0003000", x"BBBBBBBB");
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    axi_read(x"A0003000");
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    axi_write(x"A0004000", x"CCCCCCCC");
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    axi_read(x"A0004000");
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    axi_write(x"A0005000", x"DDDDDDDD");
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    axi_read(x"A0005000");
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    axi_write(x"A0006000", x"EEEEEEEE");
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    axi_read(x"A0006000");
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    axi_write(x"A0007000", x"FFFFFFFF");
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    axi_read(x"A0007000");
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    axi_write(x"A0008000", x"22222222");
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    axi_read(x"A0008000");
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    axi_write(x"A0009000", x"33333333");
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    axi_read(x"A0009000");
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    axi_write(x"A000A000", x"44444444");
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    axi_read(x"A000A000");
253
    waitclk(100);
254
 
255
    assert false report "End of simulation" severity failure;
256
 
257
  end process;
258
 
259
 
260
  -------------------------
261
  -- Unit Under Test
262
  -------------------------
263
  uut : entity work.msec_ipcore_axilite
264
  generic map(
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    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
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    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
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    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
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    C_FIFO_DEPTH      => C_FIFO_DEPTH,
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    C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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    C_FPGA_MAN        => C_FPGA_MAN,   -- xilinx, altera are valid options
272
    C_BASEADDR        => C_BASEADDR,
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    C_HIGHADDR        => C_HIGHADDR
274
  )
275
  port map(
276
    --USER ports
277
 
278
    -------------------------
279
    -- AXI4lite interface
280
    -------------------------
281
    --- Global signals
282
    S_AXI_ACLK    => S_AXI_ACLK,
283
    S_AXI_ARESETN => S_AXI_ARESETN,
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    --- Write address channel
285
    S_AXI_AWADDR  => S_AXI_AWADDR,
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    S_AXI_AWVALID => S_AXI_AWVALID,
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    S_AXI_AWREADY => S_AXI_AWREADY,
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    --- Write data channel
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    S_AXI_WDATA  => S_AXI_WDATA,
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    S_AXI_WVALID => S_AXI_WVALID,
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    S_AXI_WREADY => S_AXI_WREADY,
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    S_AXI_WSTRB  => S_AXI_WSTRB,
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    --- Write response channel
294
    S_AXI_BVALID => S_AXI_BVALID,
295
    S_AXI_BREADY => S_AXI_BREADY,
296
    S_AXI_BRESP  => S_AXI_BRESP,
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    --- Read address channel
298
    S_AXI_ARADDR  => S_AXI_ARADDR,
299
    S_AXI_ARVALID => S_AXI_ARVALID,
300
    S_AXI_ARREADY => S_AXI_ARREADY,
301
    --- Read data channel
302
    S_AXI_RDATA  => S_AXI_RDATA,
303
    S_AXI_RVALID => S_AXI_RVALID,
304
    S_AXI_RREADY => S_AXI_RREADY,
305
    S_AXI_RRESP  => S_AXI_RRESP
306
  );
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308
end arch;
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