OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 2 JonasDC
  constant nr_stages  : integer := 96;
67
  constant clk_period : time := 10 ns;
68
  signal clk          : std_logic := '0';
69
  signal reset        : std_logic := '1';
70 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
71
  file output         : text open write_mode is "out/sim_output.txt";
72 2 JonasDC
 
73
  ------------------------------------------------------------------
74
  -- Signals for multiplier core memory space
75
  ------------------------------------------------------------------
76
  signal core_rw_address   : std_logic_vector (8 downto 0);
77
  signal core_data_in      : std_logic_vector(31 downto 0);
78
  signal core_fifo_din     : std_logic_vector(31 downto 0);
79
  signal core_data_out     : std_logic_vector(31 downto 0);
80
  signal core_write_enable : std_logic;
81
  signal core_fifo_push    : std_logic;
82
  ------------------------------------------------------------------
83
  -- Signals for multiplier core control
84
  ------------------------------------------------------------------
85
  signal core_start          : std_logic;
86
  signal core_run_auto       : std_logic;
87
  signal core_p_sel          : std_logic_vector(1 downto 0);
88
  signal core_dest_op_single : std_logic_vector(1 downto 0);
89
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
90
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
91
  signal calc_time           : std_logic;
92
  ------------------------------------------------------------------
93
  -- Signals for multiplier core interrupt
94
  ------------------------------------------------------------------
95
  signal core_fifo_full   : std_logic;
96
  signal core_fifo_nopush : std_logic;
97
  signal core_ready       : std_logic;
98
  signal core_mem_collision : std_logic;
99
 
100
begin
101
 
102
------------------------------------------
103
-- Generate clk
104
------------------------------------------
105
clk_process : process
106
begin
107
  while (true) loop
108
    clk <= '0';
109
    wait for clk_period/2;
110
    clk <= '1';
111
    wait for clk_period/2;
112
  end loop;
113
end process;
114
 
115
------------------------------------------
116
-- Stimulus Process
117
------------------------------------------
118
stim_proc : process
119
  procedure waitclk(n : natural := 1) is
120
  begin
121
    for i in 1 to n loop
122
      wait until rising_edge(clk);
123
    end loop;
124
  end waitclk;
125
 
126
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
127
               variable op_data : std_logic_vector(2047 downto 0)) is
128
  begin
129
    wait until rising_edge(clk);
130
    core_rw_address <= op_sel & "000000";
131
    wait until rising_edge(clk);
132
    core_write_enable <= '1';
133
    for i in 0 to (1536/32)-1 loop
134
      assert (core_mem_collision='0')
135
        report "collision detected while writing operand!!" severity failure;
136
      case (core_p_sel) is
137
        when "11" =>
138
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
139
        when "01" =>
140
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
141
          else core_data_in <= x"00000000"; end if;
142
        when "10" =>
143
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
144
          else core_data_in <= x"00000000"; end if;
145
        when others =>
146
          core_data_in <= x"00000000";
147
      end case;
148
 
149
      wait until rising_edge(clk);
150
      core_rw_address <= core_rw_address+"000000001";
151
    end loop;
152
    core_write_enable <= '0';
153
    wait until rising_edge(clk);
154
  end loadOp;
155
 
156
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
157
                  variable op_data  : out std_logic_vector(2047 downto 0);
158
                  variable op_width : integer) is
159
  begin
160
      wait until rising_edge(clk);
161
      core_dest_op_single <= op_sel(1 downto 0);
162
      if (core_p_sel = "10") then
163
        core_rw_address <= op_sel & "010000";
164
      else
165
        core_rw_address <= op_sel & "000000";
166
      end if;
167
      waitclk(2);
168
 
169
      for i in 0 to (op_width/32)-2 loop
170
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
171
          core_rw_address <= core_rw_address+"000000001";
172
          waitclk(2);
173
      end loop;
174
      op_data(op_width-1 downto op_width-32) := core_data_out;
175
      wait until rising_edge(clk);
176
  end readOp;
177
 
178
  function ToString(constant Timeval : time) return string is
179
    variable StrPtr : line;
180
  begin
181
    write(StrPtr,Timeval);
182
    return StrPtr.all;
183
  end ToString;
184
 
185
  -- variables to read file
186
  variable L : line;
187
  variable Lw : line;
188
  variable base_width : integer;
189
  variable exponent_width : integer;
190
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
191
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
192
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
193
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
194
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
195
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
196
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
197
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
198
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
199
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
200
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
201
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
202
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
203
  variable good_value : boolean;
204
  variable param_count : integer := 0;
205
 
206
  -- constants for operand selection
207
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
208
  constant op_0 : std_logic_vector(2 downto 0) := "000";
209
  constant op_1 : std_logic_vector(2 downto 0) := "001";
210
  constant op_2 : std_logic_vector(2 downto 0) := "010";
211
  constant op_3 : std_logic_vector(2 downto 0) := "011";
212
 
213
  variable timer : time;
214
begin
215
  -- initialisation
216
  -- memory
217
  core_write_enable <= '0';
218
  core_data_in <= x"00000000";
219
  core_rw_address <= "000000000";
220
  -- fifo
221
  core_fifo_din <= x"00000000";
222
  core_fifo_push <= '0';
223
  -- control
224
  core_start <= '0';
225
  core_run_auto <= '0';
226
  core_x_sel_single <= "00";
227
  core_y_sel_single <= "01";
228
  core_dest_op_single <= "01";
229
  core_p_sel <= "11";
230
 
231
  -- Generate active high reset signal
232
  reset <= '1';
233
  waitclk(100);
234
  reset <= '0';
235
  waitclk(100);
236
 
237
  while not endfile(input) loop
238
    readline(input, L); -- read next line
239
    next when L(1)='-'; -- skip comment lines
240
    -- read input values
241
    case param_count is
242
      when 0 => -- base width
243
        read(L, base_width, good_value);
244
        assert good_value report "Can not read base width" severity failure;
245
        assert false report "Simulating exponentiation" severity note;
246
        write(Lw, string'("----------------------------------------------"));
247
        writeline(output, Lw);
248
        write(Lw, string'("--              EXPONENTIATION              --"));
249
        writeline(output, Lw);
250
        write(Lw, string'("----------------------------------------------"));
251
        writeline(output, Lw);
252
        write(Lw, string'("----- Variables used:"));
253
        writeline(output, Lw);
254
        write(Lw, string'("base width: "));
255
        write(Lw, base_width);
256
        writeline(output, Lw);
257
        case (base_width) is
258
          when 1536 => when 1024 => when 512 =>
259
          when others =>
260
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
261
            assert false report "incompatible base width!!!" severity failure;
262
        end case;
263
 
264
      when 1 => -- exponent width
265
        read(L, exponent_width, good_value);
266
        assert good_value report "Can not read exponent width" severity failure;
267
        write(Lw, string'("exponent width: "));
268
        write(Lw, exponent_width);
269
        writeline(output, Lw);
270
 
271
      when 2 => -- g0
272
        hread(L, g0(base_width-1 downto 0), good_value);
273
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
274
        write(Lw, string'("g0: "));
275
        hwrite(Lw, g0(base_width-1 downto 0));
276
        writeline(output, Lw);
277
 
278
      when 3 => -- g1
279
        hread(L, g1(base_width-1 downto 0), good_value);
280
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
281
        write(Lw, string'("g1: "));
282
        hwrite(Lw, g1(base_width-1 downto 0));
283
        writeline(output, Lw);
284
 
285
      when 4 => -- e0
286
        hread(L, e0(exponent_width-1 downto 0), good_value);
287
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
288
        write(Lw, string'("e0: "));
289
        hwrite(Lw, e0(exponent_width-1 downto 0));
290
        writeline(output, Lw);
291
 
292
      when 5 => -- e1
293
        hread(L, e1(exponent_width-1 downto 0), good_value);
294
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
295
        write(Lw, string'("e1: "));
296
        hwrite(Lw, e1(exponent_width-1 downto 0));
297
        writeline(output, Lw);
298
 
299
      when 6 => -- m
300
        hread(L, m(base_width-1 downto 0), good_value);
301
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
302
        write(Lw, string'("m:  "));
303
        hwrite(Lw, m(base_width-1 downto 0));
304
        writeline(output, Lw);
305
 
306
      when 7 => -- R^2
307
        hread(L, R2(base_width-1 downto 0), good_value);
308
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
309
        write(Lw, string'("R2: "));
310
        hwrite(Lw, R2(base_width-1 downto 0));
311
        writeline(output, Lw);
312
 
313
      when 8 => -- R
314
        hread(L, R(base_width-1 downto 0), good_value);
315
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
316
 
317
      when 9 => -- gt0
318
        hread(L, gt0(base_width-1 downto 0), good_value);
319
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
320
 
321
      when 10 => -- gt1
322
        hread(L, gt1(base_width-1 downto 0), good_value);
323
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
324
 
325
      when 11 => -- gt01
326
        hread(L, gt01(base_width-1 downto 0), good_value);
327
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
328
 
329
        -- select pipeline for all computations
330
        ----------------------------------------
331
        writeline(output, Lw);
332
        write(Lw, string'("----- Selecting pipeline: "));
333
        writeline(output, Lw);
334
        case (base_width) is
335
          when 1536 =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
336
          when 1024 =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
337
          when 512  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
338
          when others =>
339
            write(Lw, string'("  Invallid bitwidth for design"));
340
            assert false report "impossible basewidth!" severity failure;
341
        end case;
342
        writeline(output, Lw);
343
 
344
        writeline(output, Lw);
345
        write(Lw, string'("----- Writing operands:"));
346
        writeline(output, Lw);
347
 
348
        -- load the modulus
349
        --------------------
350
        loadOp(op_modulus, m); -- visual check needed
351
        write(Lw, string'("  m written"));
352
        writeline(output, Lw);
353
 
354
        -- load g0
355
        -----------
356
        loadOp(op_0, g0);
357
        -- verify
358
        readOp(op_0, data_read, base_width);
359
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
360
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
361
        else
362
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
363
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
364
        end if;
365
 
366
        -- load g1
367
        -----------
368
        loadOp(op_1, g1);
369
        -- verify
370
        readOp(op_1, data_read, base_width);
371
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
372
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
373
        else
374
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
375
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
376
        end if;
377
 
378
        -- load R2
379
        -----------
380
        loadOp(op_2, R2);
381
        -- verify
382
        readOp(op_2, data_read, base_width);
383
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
384
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
385
        else
386
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
387
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
388
        end if;
389
 
390
        -- load a=1
391
        ------------
392
        loadOp(op_3, one);
393
        -- verify
394
        readOp(op_3, data_read, base_width);
395
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
396
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
397
        else
398
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
399
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
400
        end if;
401
 
402
        writeline(output, Lw);
403
        write(Lw, string'("----- Pre-computations: "));
404
        writeline(output, Lw);
405
 
406
        -- compute gt0
407
        ---------------
408
        core_x_sel_single <= "00"; -- g0
409
        core_y_sel_single <= "10"; -- R^2
410
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
411
        wait until rising_edge(clk);
412
        timer := NOW;
413
        core_start <= '1';
414
        wait until rising_edge(clk);
415
        core_start <= '0';
416
        wait until core_ready = '1';
417
        timer := NOW-timer;
418
        waitclk(10);
419
        readOp(op_0, data_read, base_width);
420
        write(Lw, string'("  Computed gt0: "));
421
        hwrite(Lw, data_read(base_width-1 downto 0));
422
        writeline(output, Lw);
423
        write(Lw, string'("  Read gt0:     "));
424
        hwrite(Lw, gt0(base_width-1 downto 0));
425
        writeline(output, Lw);
426
        write(Lw, string'("  => calc time is "));
427
        write(Lw, string'(ToString(timer)));
428
        writeline(output, Lw);
429
        write(Lw, string'("  => expected time is "));
430
        write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
431
        writeline(output, Lw);
432
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
433
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
434
        else
435
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
436
          assert false report "gt0 is incorrect!!!" severity failure;
437
        end if;
438
 
439
        -- compute gt1
440
        ---------------
441
        core_x_sel_single <= "01"; -- g1
442
        core_y_sel_single <= "10"; -- R^2
443
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
444
        wait until rising_edge(clk);
445
        timer := NOW;
446
        core_start <= '1';
447
        wait until rising_edge(clk);
448
        core_start <= '0';
449
        wait until core_ready = '1';
450
        timer := NOW-timer;
451
        waitclk(10);
452
        readOp(op_1, data_read, base_width);
453
        write(Lw, string'("  Computed gt1: "));
454
        hwrite(Lw, data_read(base_width-1 downto 0));
455
        writeline(output, Lw);
456
        write(Lw, string'("  Read gt1:     "));
457
        hwrite(Lw, gt1(base_width-1 downto 0));
458
        writeline(output, Lw);
459
        write(Lw, string'("  => calc time is "));
460
        write(Lw, string'(ToString(timer)));
461
        writeline(output, Lw);
462
        write(Lw, string'("  => expected time is "));
463
        write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
464
        writeline(output, Lw);
465
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
466
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
467
        else
468
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
469
          assert false report "gt1 is incorrect!!!" severity failure;
470
        end if;
471
 
472
        -- compute a
473
        -------------
474
        core_x_sel_single <= "10"; -- R^2
475
        core_y_sel_single <= "11"; -- 1
476
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
477
        wait until rising_edge(clk);
478
        core_start <= '1';
479
        timer := NOW;
480
        wait until rising_edge(clk);
481
        core_start <= '0';
482
        wait until core_ready = '1';
483
        timer := NOW-timer;
484
        waitclk(10);
485
        readOp(op_3, data_read, base_width);
486
        write(Lw, string'("  Computed a=(R)mod m: "));
487
        hwrite(Lw, data_read(base_width-1 downto 0));
488
        writeline(output, Lw);
489
        write(Lw, string'("  Read (R)mod m:       "));
490
        hwrite(Lw, R(base_width-1 downto 0));
491
        writeline(output, Lw);
492
        write(Lw, string'("  => calc time is "));
493
        write(Lw, string'(ToString(timer)));
494
        writeline(output, Lw);
495
        write(Lw, string'("  => expected time is "));
496
        write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
497
        writeline(output, Lw);
498
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
499
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
500
        else
501
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
502
          assert false report "(R)mod m is incorrect!!!" severity failure;
503
        end if;
504
 
505
        -- compute gt01
506
        ---------------
507
        core_x_sel_single <= "00"; -- gt0
508
        core_y_sel_single <= "01"; -- gt1
509
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
510
        wait until rising_edge(clk);
511
        core_start <= '1';
512
        timer := NOW;
513
        wait until rising_edge(clk);
514
        core_start <= '0';
515
        wait until core_ready = '1';
516
        timer := NOW-timer;
517
        waitclk(10);
518
        readOp(op_2, data_read, base_width);
519
        write(Lw, string'("  Computed gt01: "));
520
        hwrite(Lw, data_read(base_width-1 downto 0));
521
        writeline(output, Lw);
522
        write(Lw, string'("  Read gt01:     "));
523
        hwrite(Lw, gt01(base_width-1 downto 0));
524
        writeline(output, Lw);
525
        write(Lw, string'("  => calc time is "));
526
        write(Lw, string'(ToString(timer)));
527
        writeline(output, Lw);
528
        write(Lw, string'("  => expected time is "));
529
        write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
530
        writeline(output, Lw);
531
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
532
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
533
        else
534
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
535
          assert false report "gt01 is incorrect!!!" severity failure;
536
        end if;
537
 
538
        -- load exponent fifo
539
        ----------------------
540
        writeline(output, Lw);
541
        write(Lw, string'("----- Loading exponent fifo: "));
542
        writeline(output, Lw);
543
        for i in (exponent_width/16)-1 downto 0 loop
544
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
545
          wait until rising_edge(clk);
546
          core_fifo_push <= '1';
547
          wait until rising_edge(clk);
548
          assert (core_fifo_full='0' and core_fifo_nopush='0')
549
            report "Fifo error, full or nopush" severity failure;
550
          core_fifo_push <= '0';
551
          wait until rising_edge(clk);
552
        end loop;
553
        waitclk(10);
554 3 JonasDC
        write(Lw, string'("  => Done"));
555 2 JonasDC
        writeline(output, Lw);
556
 
557
        -- start exponentiation
558
        ------------------------
559
        writeline(output, Lw);
560
        write(Lw, string'("----- Starting exponentiation: "));
561
        writeline(output, Lw);
562
        core_run_auto <= '1';
563
        wait until rising_edge(clk);
564
        timer := NOW;
565
        core_start <= '1';
566
        wait until rising_edge(clk);
567
        core_start <= '0';
568
        wait until core_ready='1';
569
        timer := NOW-timer;
570
        waitclk(10);
571
        write(Lw, string'("  => calc time is "));
572
        write(Lw, string'(ToString(timer)));
573
        writeline(output, Lw);
574
        write(Lw, string'("  => expected time is "));
575
        write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
576
        writeline(output, Lw);
577
        write(Lw, string'("  => Done"));
578
        core_run_auto <= '0';
579
        writeline(output, Lw);
580
 
581
        -- post-computations
582
        ---------------------
583
        writeline(output, Lw);
584
        write(Lw, string'("----- Post-computations: "));
585
        writeline(output, Lw);
586
        -- load in 1 to operand 2
587
        loadOp(op_2, one);
588
        -- verify
589
        readOp(op_2, data_read, base_width);
590
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
591
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
592
        else
593
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
594
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
595
        end if;
596
        -- compute result
597
        core_x_sel_single <= "11"; -- a
598
        core_y_sel_single <= "10"; -- 1
599
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
600
        wait until rising_edge(clk);
601
        timer := NOW;
602
        core_start <= '1';
603
        wait until rising_edge(clk);
604
        core_start <= '0';
605
        wait until core_ready = '1';
606
        timer := NOW-timer;
607
        waitclk(10);
608
        readOp(op_3, data_read, base_width);
609
        write(Lw, string'("  Computed result: "));
610
        hwrite(Lw, data_read(base_width-1 downto 0));
611
        writeline(output, Lw);
612
        write(Lw, string'("  => calc time is "));
613
        write(Lw, string'(ToString(timer)));
614
        writeline(output, Lw);
615
        write(Lw, string'("  => expected time is "));
616
        write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
617
        writeline(output, Lw);
618
 
619
      when 12 => -- check with result
620
        hread(L, result(base_width-1 downto 0), good_value);
621
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
622
        writeline(output, Lw);
623
        write(Lw, string'("----- verifying result: "));
624
        writeline(output, Lw);
625
        write(Lw, string'("  Read result:     "));
626
        hwrite(Lw, result(base_width-1 downto 0));
627
        writeline(output, Lw);
628
        write(Lw, string'("  Computed result: "));
629
        hwrite(Lw, data_read(base_width-1 downto 0));
630
        writeline(output, Lw);
631
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
632
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
633
        else
634
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
635
          assert false report "result is incorrect!!!" severity failure;
636
        end if;
637
        writeline(output, Lw);
638
 
639
      when others =>
640
        assert false report "undefined state!" severity failure;
641
    end case;
642
 
643
    if (param_count = 12) then
644
      param_count := 0;
645
    else
646
      param_count := param_count+1;
647
    end if;
648
  end loop;
649
 
650
  wait for 1 us;
651
  assert false report "End of simulation" severity failure;
652
 
653
end process;
654
 
655
------------------------------------------
656
-- Multiplier core instance
657
------------------------------------------
658 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
659 2 JonasDC
port map(
660
  clk   => clk,
661
  reset => reset,
662
-- operand memory interface (plb shared memory)
663
  write_enable => core_write_enable,
664
  data_in      => core_data_in,
665
  rw_address   => core_rw_address,
666
  data_out     => core_data_out,
667
  collision    => core_mem_collision,
668
-- op_sel fifo interface
669
  fifo_din    => core_fifo_din,
670
  fifo_push   => core_fifo_push,
671
  fifo_full   => core_fifo_full,
672
  fifo_nopush => core_fifo_nopush,
673
-- ctrl signals
674
  start          => core_start,
675
  run_auto       => core_run_auto,
676
  ready          => core_ready,
677
  x_sel_single   => core_x_sel_single,
678
  y_sel_single   => core_y_sel_single,
679
  dest_op_single => core_dest_op_single,
680
  p_sel          => core_p_sel,
681
  calc_time      => calc_time
682
);
683
 
684
end test;

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.