OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 2 JonasDC
  constant clk_period : time := 10 ns;
67
  signal clk          : std_logic := '0';
68
  signal reset        : std_logic := '1';
69 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
70
  file output         : text open write_mode is "out/sim_output.txt";
71 2 JonasDC
 
72
  ------------------------------------------------------------------
73
  -- Signals for multiplier core memory space
74
  ------------------------------------------------------------------
75
  signal core_rw_address   : std_logic_vector (8 downto 0);
76
  signal core_data_in      : std_logic_vector(31 downto 0);
77
  signal core_fifo_din     : std_logic_vector(31 downto 0);
78
  signal core_data_out     : std_logic_vector(31 downto 0);
79
  signal core_write_enable : std_logic;
80
  signal core_fifo_push    : std_logic;
81
  ------------------------------------------------------------------
82
  -- Signals for multiplier core control
83
  ------------------------------------------------------------------
84
  signal core_start          : std_logic;
85
  signal core_run_auto       : std_logic;
86
  signal core_p_sel          : std_logic_vector(1 downto 0);
87
  signal core_dest_op_single : std_logic_vector(1 downto 0);
88
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
89
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
90
  signal calc_time           : std_logic;
91
  ------------------------------------------------------------------
92
  -- Signals for multiplier core interrupt
93
  ------------------------------------------------------------------
94
  signal core_fifo_full   : std_logic;
95
  signal core_fifo_nopush : std_logic;
96
  signal core_ready       : std_logic;
97
  signal core_mem_collision : std_logic;
98
 
99
begin
100
 
101
------------------------------------------
102
-- Generate clk
103
------------------------------------------
104
clk_process : process
105
begin
106
  while (true) loop
107
    clk <= '0';
108
    wait for clk_period/2;
109
    clk <= '1';
110
    wait for clk_period/2;
111
  end loop;
112
end process;
113
 
114
------------------------------------------
115
-- Stimulus Process
116
------------------------------------------
117
stim_proc : process
118
  procedure waitclk(n : natural := 1) is
119
  begin
120
    for i in 1 to n loop
121
      wait until rising_edge(clk);
122
    end loop;
123
  end waitclk;
124
 
125
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
126
               variable op_data : std_logic_vector(2047 downto 0)) is
127
  begin
128
    wait until rising_edge(clk);
129
    core_rw_address <= op_sel & "000000";
130
    wait until rising_edge(clk);
131
    core_write_enable <= '1';
132
    for i in 0 to (1536/32)-1 loop
133
      assert (core_mem_collision='0')
134
        report "collision detected while writing operand!!" severity failure;
135
      case (core_p_sel) is
136
        when "11" =>
137
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
138
        when "01" =>
139
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
140
          else core_data_in <= x"00000000"; end if;
141
        when "10" =>
142
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
143
          else core_data_in <= x"00000000"; end if;
144
        when others =>
145
          core_data_in <= x"00000000";
146
      end case;
147
 
148
      wait until rising_edge(clk);
149
      core_rw_address <= core_rw_address+"000000001";
150
    end loop;
151
    core_write_enable <= '0';
152
    wait until rising_edge(clk);
153
  end loadOp;
154
 
155
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
156
                  variable op_data  : out std_logic_vector(2047 downto 0);
157
                  variable op_width : integer) is
158
  begin
159
      wait until rising_edge(clk);
160
      core_dest_op_single <= op_sel(1 downto 0);
161
      if (core_p_sel = "10") then
162
        core_rw_address <= op_sel & "010000";
163
      else
164
        core_rw_address <= op_sel & "000000";
165
      end if;
166
      waitclk(2);
167
 
168
      for i in 0 to (op_width/32)-2 loop
169
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
170
          core_rw_address <= core_rw_address+"000000001";
171
          waitclk(2);
172
      end loop;
173
      op_data(op_width-1 downto op_width-32) := core_data_out;
174
      wait until rising_edge(clk);
175
  end readOp;
176
 
177
  function ToString(constant Timeval : time) return string is
178
    variable StrPtr : line;
179
  begin
180
    write(StrPtr,Timeval);
181
    return StrPtr.all;
182
  end ToString;
183
 
184
  -- variables to read file
185
  variable L : line;
186
  variable Lw : line;
187
  variable base_width : integer;
188
  variable exponent_width : integer;
189
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
190
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
191
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
192
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
193
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
194
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
195
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
196
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
197
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
198
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
199
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
200
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
201
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
202
  variable good_value : boolean;
203
  variable param_count : integer := 0;
204
 
205
  -- constants for operand selection
206
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
207
  constant op_0 : std_logic_vector(2 downto 0) := "000";
208
  constant op_1 : std_logic_vector(2 downto 0) := "001";
209
  constant op_2 : std_logic_vector(2 downto 0) := "010";
210
  constant op_3 : std_logic_vector(2 downto 0) := "011";
211
 
212
  variable timer : time;
213
begin
214
  -- initialisation
215
  -- memory
216
  core_write_enable <= '0';
217
  core_data_in <= x"00000000";
218
  core_rw_address <= "000000000";
219
  -- fifo
220
  core_fifo_din <= x"00000000";
221
  core_fifo_push <= '0';
222
  -- control
223
  core_start <= '0';
224
  core_run_auto <= '0';
225
  core_x_sel_single <= "00";
226
  core_y_sel_single <= "01";
227
  core_dest_op_single <= "01";
228
  core_p_sel <= "11";
229
 
230
  -- Generate active high reset signal
231
  reset <= '1';
232
  waitclk(100);
233
  reset <= '0';
234
  waitclk(100);
235
 
236
  while not endfile(input) loop
237
    readline(input, L); -- read next line
238
    next when L(1)='-'; -- skip comment lines
239
    -- read input values
240
    case param_count is
241
      when 0 => -- base width
242
        read(L, base_width, good_value);
243
        assert good_value report "Can not read base width" severity failure;
244
        assert false report "Simulating exponentiation" severity note;
245
        write(Lw, string'("----------------------------------------------"));
246
        writeline(output, Lw);
247
        write(Lw, string'("--              EXPONENTIATION              --"));
248
        writeline(output, Lw);
249
        write(Lw, string'("----------------------------------------------"));
250
        writeline(output, Lw);
251
        write(Lw, string'("----- Variables used:"));
252
        writeline(output, Lw);
253
        write(Lw, string'("base width: "));
254
        write(Lw, base_width);
255
        writeline(output, Lw);
256
        case (base_width) is
257 37 JonasDC
          when nr_bits_total => when nr_bits_high => when nr_bits_low =>
258 2 JonasDC
          when others =>
259
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
260
            assert false report "incompatible base width!!!" severity failure;
261
        end case;
262
 
263
      when 1 => -- exponent width
264
        read(L, exponent_width, good_value);
265
        assert good_value report "Can not read exponent width" severity failure;
266
        write(Lw, string'("exponent width: "));
267
        write(Lw, exponent_width);
268
        writeline(output, Lw);
269
 
270
      when 2 => -- g0
271
        hread(L, g0(base_width-1 downto 0), good_value);
272
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
273
        write(Lw, string'("g0: "));
274
        hwrite(Lw, g0(base_width-1 downto 0));
275
        writeline(output, Lw);
276
 
277
      when 3 => -- g1
278
        hread(L, g1(base_width-1 downto 0), good_value);
279
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
280
        write(Lw, string'("g1: "));
281
        hwrite(Lw, g1(base_width-1 downto 0));
282
        writeline(output, Lw);
283
 
284
      when 4 => -- e0
285
        hread(L, e0(exponent_width-1 downto 0), good_value);
286
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
287
        write(Lw, string'("e0: "));
288
        hwrite(Lw, e0(exponent_width-1 downto 0));
289
        writeline(output, Lw);
290
 
291
      when 5 => -- e1
292
        hread(L, e1(exponent_width-1 downto 0), good_value);
293
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
294
        write(Lw, string'("e1: "));
295
        hwrite(Lw, e1(exponent_width-1 downto 0));
296
        writeline(output, Lw);
297
 
298
      when 6 => -- m
299
        hread(L, m(base_width-1 downto 0), good_value);
300
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
301
        write(Lw, string'("m:  "));
302
        hwrite(Lw, m(base_width-1 downto 0));
303
        writeline(output, Lw);
304
 
305
      when 7 => -- R^2
306
        hread(L, R2(base_width-1 downto 0), good_value);
307
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
308
        write(Lw, string'("R2: "));
309
        hwrite(Lw, R2(base_width-1 downto 0));
310
        writeline(output, Lw);
311
 
312
      when 8 => -- R
313
        hread(L, R(base_width-1 downto 0), good_value);
314
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
315
 
316
      when 9 => -- gt0
317
        hread(L, gt0(base_width-1 downto 0), good_value);
318
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
319
 
320
      when 10 => -- gt1
321
        hread(L, gt1(base_width-1 downto 0), good_value);
322
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
323
 
324
      when 11 => -- gt01
325
        hread(L, gt01(base_width-1 downto 0), good_value);
326
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
327
 
328
        -- select pipeline for all computations
329
        ----------------------------------------
330
        writeline(output, Lw);
331
        write(Lw, string'("----- Selecting pipeline: "));
332
        writeline(output, Lw);
333
        case (base_width) is
334 37 JonasDC
          when nr_bits_total =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
335
          when nr_bits_high =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
336
          when nr_bits_low  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
337 2 JonasDC
          when others =>
338
            write(Lw, string'("  Invallid bitwidth for design"));
339
            assert false report "impossible basewidth!" severity failure;
340
        end case;
341
        writeline(output, Lw);
342
 
343
        writeline(output, Lw);
344
        write(Lw, string'("----- Writing operands:"));
345
        writeline(output, Lw);
346
 
347
        -- load the modulus
348
        --------------------
349
        loadOp(op_modulus, m); -- visual check needed
350
        write(Lw, string'("  m written"));
351
        writeline(output, Lw);
352
 
353
        -- load g0
354
        -----------
355
        loadOp(op_0, g0);
356
        -- verify
357
        readOp(op_0, data_read, base_width);
358
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
359
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
360
        else
361
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
362
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
363
        end if;
364
 
365
        -- load g1
366
        -----------
367
        loadOp(op_1, g1);
368
        -- verify
369
        readOp(op_1, data_read, base_width);
370
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
371
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
372
        else
373
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
374
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
375
        end if;
376
 
377
        -- load R2
378
        -----------
379
        loadOp(op_2, R2);
380
        -- verify
381
        readOp(op_2, data_read, base_width);
382
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
383
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
384
        else
385
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
386
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
387
        end if;
388
 
389
        -- load a=1
390
        ------------
391
        loadOp(op_3, one);
392
        -- verify
393
        readOp(op_3, data_read, base_width);
394
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
395
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
396
        else
397
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
398
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
399
        end if;
400
 
401
        writeline(output, Lw);
402
        write(Lw, string'("----- Pre-computations: "));
403
        writeline(output, Lw);
404
 
405
        -- compute gt0
406
        ---------------
407
        core_x_sel_single <= "00"; -- g0
408
        core_y_sel_single <= "10"; -- R^2
409
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
410
        wait until rising_edge(clk);
411
        timer := NOW;
412
        core_start <= '1';
413
        wait until rising_edge(clk);
414
        core_start <= '0';
415
        wait until core_ready = '1';
416
        timer := NOW-timer;
417
        waitclk(10);
418
        readOp(op_0, data_read, base_width);
419
        write(Lw, string'("  Computed gt0: "));
420
        hwrite(Lw, data_read(base_width-1 downto 0));
421
        writeline(output, Lw);
422
        write(Lw, string'("  Read gt0:     "));
423
        hwrite(Lw, gt0(base_width-1 downto 0));
424
        writeline(output, Lw);
425
        write(Lw, string'("  => calc time is "));
426
        write(Lw, string'(ToString(timer)));
427
        writeline(output, Lw);
428
        write(Lw, string'("  => expected time is "));
429 37 JonasDC
        write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
430 2 JonasDC
        writeline(output, Lw);
431
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
432
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
433
        else
434
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
435
          assert false report "gt0 is incorrect!!!" severity failure;
436
        end if;
437
 
438
        -- compute gt1
439
        ---------------
440
        core_x_sel_single <= "01"; -- g1
441
        core_y_sel_single <= "10"; -- R^2
442
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
443
        wait until rising_edge(clk);
444
        timer := NOW;
445
        core_start <= '1';
446
        wait until rising_edge(clk);
447
        core_start <= '0';
448
        wait until core_ready = '1';
449
        timer := NOW-timer;
450
        waitclk(10);
451
        readOp(op_1, data_read, base_width);
452
        write(Lw, string'("  Computed gt1: "));
453
        hwrite(Lw, data_read(base_width-1 downto 0));
454
        writeline(output, Lw);
455
        write(Lw, string'("  Read gt1:     "));
456
        hwrite(Lw, gt1(base_width-1 downto 0));
457
        writeline(output, Lw);
458
        write(Lw, string'("  => calc time is "));
459
        write(Lw, string'(ToString(timer)));
460
        writeline(output, Lw);
461
        write(Lw, string'("  => expected time is "));
462 37 JonasDC
        write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
463 2 JonasDC
        writeline(output, Lw);
464
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
465
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
466
        else
467
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
468
          assert false report "gt1 is incorrect!!!" severity failure;
469
        end if;
470
 
471
        -- compute a
472
        -------------
473
        core_x_sel_single <= "10"; -- R^2
474
        core_y_sel_single <= "11"; -- 1
475
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
476
        wait until rising_edge(clk);
477
        core_start <= '1';
478
        timer := NOW;
479
        wait until rising_edge(clk);
480
        core_start <= '0';
481
        wait until core_ready = '1';
482
        timer := NOW-timer;
483
        waitclk(10);
484
        readOp(op_3, data_read, base_width);
485
        write(Lw, string'("  Computed a=(R)mod m: "));
486
        hwrite(Lw, data_read(base_width-1 downto 0));
487
        writeline(output, Lw);
488
        write(Lw, string'("  Read (R)mod m:       "));
489
        hwrite(Lw, R(base_width-1 downto 0));
490
        writeline(output, Lw);
491
        write(Lw, string'("  => calc time is "));
492
        write(Lw, string'(ToString(timer)));
493
        writeline(output, Lw);
494
        write(Lw, string'("  => expected time is "));
495 37 JonasDC
        write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
496 2 JonasDC
        writeline(output, Lw);
497
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
498
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
499
        else
500
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
501
          assert false report "(R)mod m is incorrect!!!" severity failure;
502
        end if;
503
 
504
        -- compute gt01
505
        ---------------
506
        core_x_sel_single <= "00"; -- gt0
507
        core_y_sel_single <= "01"; -- gt1
508
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
509
        wait until rising_edge(clk);
510
        core_start <= '1';
511
        timer := NOW;
512
        wait until rising_edge(clk);
513
        core_start <= '0';
514
        wait until core_ready = '1';
515
        timer := NOW-timer;
516
        waitclk(10);
517
        readOp(op_2, data_read, base_width);
518
        write(Lw, string'("  Computed gt01: "));
519
        hwrite(Lw, data_read(base_width-1 downto 0));
520
        writeline(output, Lw);
521
        write(Lw, string'("  Read gt01:     "));
522
        hwrite(Lw, gt01(base_width-1 downto 0));
523
        writeline(output, Lw);
524
        write(Lw, string'("  => calc time is "));
525
        write(Lw, string'(ToString(timer)));
526
        writeline(output, Lw);
527
        write(Lw, string'("  => expected time is "));
528 37 JonasDC
        write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
529 2 JonasDC
        writeline(output, Lw);
530
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
531
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
532
        else
533
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
534
          assert false report "gt01 is incorrect!!!" severity failure;
535
        end if;
536
 
537
        -- load exponent fifo
538
        ----------------------
539
        writeline(output, Lw);
540
        write(Lw, string'("----- Loading exponent fifo: "));
541
        writeline(output, Lw);
542
        for i in (exponent_width/16)-1 downto 0 loop
543
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
544
          wait until rising_edge(clk);
545
          core_fifo_push <= '1';
546
          wait until rising_edge(clk);
547
          assert (core_fifo_full='0' and core_fifo_nopush='0')
548
            report "Fifo error, full or nopush" severity failure;
549
          core_fifo_push <= '0';
550
          wait until rising_edge(clk);
551
        end loop;
552
        waitclk(10);
553 3 JonasDC
        write(Lw, string'("  => Done"));
554 2 JonasDC
        writeline(output, Lw);
555
 
556
        -- start exponentiation
557
        ------------------------
558
        writeline(output, Lw);
559
        write(Lw, string'("----- Starting exponentiation: "));
560
        writeline(output, Lw);
561
        core_run_auto <= '1';
562
        wait until rising_edge(clk);
563
        timer := NOW;
564
        core_start <= '1';
565
        wait until rising_edge(clk);
566
        core_start <= '0';
567
        wait until core_ready='1';
568
        timer := NOW-timer;
569
        waitclk(10);
570
        write(Lw, string'("  => calc time is "));
571
        write(Lw, string'(ToString(timer)));
572
        writeline(output, Lw);
573
        write(Lw, string'("  => expected time is "));
574 37 JonasDC
        write(Lw, ((nr_stages_total+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
575 2 JonasDC
        writeline(output, Lw);
576
        write(Lw, string'("  => Done"));
577
        core_run_auto <= '0';
578
        writeline(output, Lw);
579
 
580
        -- post-computations
581
        ---------------------
582
        writeline(output, Lw);
583
        write(Lw, string'("----- Post-computations: "));
584
        writeline(output, Lw);
585
        -- load in 1 to operand 2
586
        loadOp(op_2, one);
587
        -- verify
588
        readOp(op_2, data_read, base_width);
589
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
590
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
591
        else
592
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
593
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
594
        end if;
595
        -- compute result
596
        core_x_sel_single <= "11"; -- a
597
        core_y_sel_single <= "10"; -- 1
598
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
599
        wait until rising_edge(clk);
600
        timer := NOW;
601
        core_start <= '1';
602
        wait until rising_edge(clk);
603
        core_start <= '0';
604
        wait until core_ready = '1';
605
        timer := NOW-timer;
606
        waitclk(10);
607
        readOp(op_3, data_read, base_width);
608
        write(Lw, string'("  Computed result: "));
609
        hwrite(Lw, data_read(base_width-1 downto 0));
610
        writeline(output, Lw);
611
        write(Lw, string'("  => calc time is "));
612
        write(Lw, string'(ToString(timer)));
613
        writeline(output, Lw);
614
        write(Lw, string'("  => expected time is "));
615 37 JonasDC
        write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
616 2 JonasDC
        writeline(output, Lw);
617
 
618
      when 12 => -- check with result
619
        hread(L, result(base_width-1 downto 0), good_value);
620
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
621
        writeline(output, Lw);
622
        write(Lw, string'("----- verifying result: "));
623
        writeline(output, Lw);
624
        write(Lw, string'("  Read result:     "));
625
        hwrite(Lw, result(base_width-1 downto 0));
626
        writeline(output, Lw);
627
        write(Lw, string'("  Computed result: "));
628
        hwrite(Lw, data_read(base_width-1 downto 0));
629
        writeline(output, Lw);
630
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
631
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
632
        else
633
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
634
          assert false report "result is incorrect!!!" severity failure;
635
        end if;
636
        writeline(output, Lw);
637
 
638
      when others =>
639
        assert false report "undefined state!" severity failure;
640
    end case;
641
 
642
    if (param_count = 12) then
643
      param_count := 0;
644
    else
645
      param_count := param_count+1;
646
    end if;
647
  end loop;
648
 
649
  wait for 1 us;
650
  assert false report "End of simulation" severity failure;
651
 
652
end process;
653
 
654
------------------------------------------
655
-- Multiplier core instance
656
------------------------------------------
657 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
658 2 JonasDC
port map(
659
  clk   => clk,
660
  reset => reset,
661
-- operand memory interface (plb shared memory)
662
  write_enable => core_write_enable,
663
  data_in      => core_data_in,
664
  rw_address   => core_rw_address,
665
  data_out     => core_data_out,
666
  collision    => core_mem_collision,
667
-- op_sel fifo interface
668
  fifo_din    => core_fifo_din,
669
  fifo_push   => core_fifo_push,
670
  fifo_full   => core_fifo_full,
671
  fifo_nopush => core_fifo_nopush,
672
-- ctrl signals
673
  start          => core_start,
674
  run_auto       => core_run_auto,
675
  ready          => core_ready,
676
  x_sel_single   => core_x_sel_single,
677
  y_sel_single   => core_y_sel_single,
678
  dest_op_single => core_dest_op_single,
679
  p_sel          => core_p_sel,
680
  calc_time      => calc_time
681
);
682
 
683
end test;

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.