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1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 43 JonasDC
  constant CLK_PERIOD : time := 10 ns;
67 2 JonasDC
  signal clk          : std_logic := '0';
68
  signal reset        : std_logic := '1';
69 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
70
  file output         : text open write_mode is "out/sim_output.txt";
71 2 JonasDC
 
72
  ------------------------------------------------------------------
73 43 JonasDC
  -- Core parameters
74
  ------------------------------------------------------------------
75
  constant C_NR_BITS_TOTAL   : integer := 1536;
76
  constant C_NR_STAGES_TOTAL : integer := 96;
77
  constant C_NR_STAGES_LOW   : integer := 32;
78 70 JonasDC
  constant C_SPLIT_PIPELINE  : boolean := true;
79
  constant C_NR_OP           : integer := 4;  -- leave on 4 for simulation
80
  constant C_NR_M            : integer := 2;  -- leave on 2 for simulation
81
  constant C_FIFO_DEPTH      : integer := 32; -- set to (maximum exponent width)/16
82
  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
83
  constant C_DEVICE          : string  := "xilinx";  -- xilinx, altera are valid options
84 43 JonasDC
 
85
  -- extra calculated constants
86
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
87
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
88
 
89
  ------------------------------------------------------------------
90 2 JonasDC
  -- Signals for multiplier core memory space
91
  ------------------------------------------------------------------
92
  signal core_rw_address   : std_logic_vector (8 downto 0);
93
  signal core_data_in      : std_logic_vector(31 downto 0);
94
  signal core_fifo_din     : std_logic_vector(31 downto 0);
95
  signal core_data_out     : std_logic_vector(31 downto 0);
96
  signal core_write_enable : std_logic;
97
  signal core_fifo_push    : std_logic;
98
  ------------------------------------------------------------------
99
  -- Signals for multiplier core control
100
  ------------------------------------------------------------------
101
  signal core_start          : std_logic;
102 46 JonasDC
  signal core_exp_m          : std_logic;
103 2 JonasDC
  signal core_p_sel          : std_logic_vector(1 downto 0);
104
  signal core_dest_op_single : std_logic_vector(1 downto 0);
105
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
106
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
107
  signal calc_time           : std_logic;
108
  ------------------------------------------------------------------
109
  -- Signals for multiplier core interrupt
110
  ------------------------------------------------------------------
111
  signal core_fifo_full   : std_logic;
112
  signal core_fifo_nopush : std_logic;
113
  signal core_ready       : std_logic;
114
  signal core_mem_collision : std_logic;
115
 
116
begin
117
 
118
------------------------------------------
119
-- Generate clk
120
------------------------------------------
121
clk_process : process
122
begin
123
  while (true) loop
124
    clk <= '0';
125 43 JonasDC
    wait for CLK_PERIOD/2;
126 2 JonasDC
    clk <= '1';
127 43 JonasDC
    wait for CLK_PERIOD/2;
128 2 JonasDC
  end loop;
129
end process;
130
 
131
------------------------------------------
132
-- Stimulus Process
133
------------------------------------------
134
stim_proc : process
135
  procedure waitclk(n : natural := 1) is
136
  begin
137
    for i in 1 to n loop
138
      wait until rising_edge(clk);
139
    end loop;
140
  end waitclk;
141
 
142
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
143
               variable op_data : std_logic_vector(2047 downto 0)) is
144
  begin
145
    wait until rising_edge(clk);
146
    core_rw_address <= op_sel & "000000";
147
    wait until rising_edge(clk);
148
    core_write_enable <= '1';
149
    for i in 0 to (1536/32)-1 loop
150
      assert (core_mem_collision='0')
151
        report "collision detected while writing operand!!" severity failure;
152
      case (core_p_sel) is
153
        when "11" =>
154
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
155
        when "01" =>
156
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
157
          else core_data_in <= x"00000000"; end if;
158
        when "10" =>
159
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
160
          else core_data_in <= x"00000000"; end if;
161
        when others =>
162
          core_data_in <= x"00000000";
163
      end case;
164
 
165
      wait until rising_edge(clk);
166
      core_rw_address <= core_rw_address+"000000001";
167
    end loop;
168
    core_write_enable <= '0';
169
    wait until rising_edge(clk);
170
  end loadOp;
171
 
172
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
173
                  variable op_data  : out std_logic_vector(2047 downto 0);
174
                  variable op_width : integer) is
175
  begin
176
      wait until rising_edge(clk);
177
      core_dest_op_single <= op_sel(1 downto 0);
178
      if (core_p_sel = "10") then
179
        core_rw_address <= op_sel & "010000";
180
      else
181
        core_rw_address <= op_sel & "000000";
182
      end if;
183
      waitclk(2);
184
 
185
      for i in 0 to (op_width/32)-2 loop
186
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
187
          core_rw_address <= core_rw_address+"000000001";
188
          waitclk(2);
189
      end loop;
190
      op_data(op_width-1 downto op_width-32) := core_data_out;
191
      wait until rising_edge(clk);
192
  end readOp;
193
 
194
  function ToString(constant Timeval : time) return string is
195
    variable StrPtr : line;
196
  begin
197
    write(StrPtr,Timeval);
198
    return StrPtr.all;
199
  end ToString;
200
 
201
  -- variables to read file
202
  variable L : line;
203
  variable Lw : line;
204
  variable base_width : integer;
205
  variable exponent_width : integer;
206
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
207
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
208
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
209
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
210
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
211
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
212
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
213
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
214
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
215
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
216
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
217
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
218
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
219
  variable good_value : boolean;
220
  variable param_count : integer := 0;
221
 
222
  -- constants for operand selection
223
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
224
  constant op_0 : std_logic_vector(2 downto 0) := "000";
225
  constant op_1 : std_logic_vector(2 downto 0) := "001";
226
  constant op_2 : std_logic_vector(2 downto 0) := "010";
227
  constant op_3 : std_logic_vector(2 downto 0) := "011";
228
 
229
  variable timer : time;
230
begin
231
  -- initialisation
232
  -- memory
233
  core_write_enable <= '0';
234
  core_data_in <= x"00000000";
235
  core_rw_address <= "000000000";
236
  -- fifo
237
  core_fifo_din <= x"00000000";
238
  core_fifo_push <= '0';
239
  -- control
240
  core_start <= '0';
241 46 JonasDC
  core_exp_m <= '0';
242 2 JonasDC
  core_x_sel_single <= "00";
243
  core_y_sel_single <= "01";
244
  core_dest_op_single <= "01";
245
  core_p_sel <= "11";
246
 
247
  -- Generate active high reset signal
248
  reset <= '1';
249
  waitclk(100);
250
  reset <= '0';
251
  waitclk(100);
252
 
253
  while not endfile(input) loop
254
    readline(input, L); -- read next line
255
    next when L(1)='-'; -- skip comment lines
256
    -- read input values
257
    case param_count is
258
      when 0 => -- base width
259
        read(L, base_width, good_value);
260
        assert good_value report "Can not read base width" severity failure;
261
        assert false report "Simulating exponentiation" severity note;
262
        write(Lw, string'("----------------------------------------------"));
263
        writeline(output, Lw);
264
        write(Lw, string'("--              EXPONENTIATION              --"));
265
        writeline(output, Lw);
266
        write(Lw, string'("----------------------------------------------"));
267
        writeline(output, Lw);
268
        write(Lw, string'("----- Variables used:"));
269
        writeline(output, Lw);
270
        write(Lw, string'("base width: "));
271
        write(Lw, base_width);
272
        writeline(output, Lw);
273
        case (base_width) is
274 43 JonasDC
          when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
275 2 JonasDC
          when others =>
276
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
277
            assert false report "incompatible base width!!!" severity failure;
278
        end case;
279
 
280
      when 1 => -- exponent width
281
        read(L, exponent_width, good_value);
282
        assert good_value report "Can not read exponent width" severity failure;
283
        write(Lw, string'("exponent width: "));
284
        write(Lw, exponent_width);
285
        writeline(output, Lw);
286
 
287
      when 2 => -- g0
288
        hread(L, g0(base_width-1 downto 0), good_value);
289
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
290
        write(Lw, string'("g0: "));
291
        hwrite(Lw, g0(base_width-1 downto 0));
292
        writeline(output, Lw);
293
 
294
      when 3 => -- g1
295
        hread(L, g1(base_width-1 downto 0), good_value);
296
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
297
        write(Lw, string'("g1: "));
298
        hwrite(Lw, g1(base_width-1 downto 0));
299
        writeline(output, Lw);
300
 
301
      when 4 => -- e0
302
        hread(L, e0(exponent_width-1 downto 0), good_value);
303
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
304
        write(Lw, string'("e0: "));
305
        hwrite(Lw, e0(exponent_width-1 downto 0));
306
        writeline(output, Lw);
307
 
308
      when 5 => -- e1
309
        hread(L, e1(exponent_width-1 downto 0), good_value);
310
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
311
        write(Lw, string'("e1: "));
312
        hwrite(Lw, e1(exponent_width-1 downto 0));
313
        writeline(output, Lw);
314
 
315
      when 6 => -- m
316
        hread(L, m(base_width-1 downto 0), good_value);
317
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
318
        write(Lw, string'("m:  "));
319
        hwrite(Lw, m(base_width-1 downto 0));
320
        writeline(output, Lw);
321
 
322
      when 7 => -- R^2
323
        hread(L, R2(base_width-1 downto 0), good_value);
324
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
325
        write(Lw, string'("R2: "));
326
        hwrite(Lw, R2(base_width-1 downto 0));
327
        writeline(output, Lw);
328
 
329
      when 8 => -- R
330
        hread(L, R(base_width-1 downto 0), good_value);
331
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
332
 
333
      when 9 => -- gt0
334
        hread(L, gt0(base_width-1 downto 0), good_value);
335
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
336
 
337
      when 10 => -- gt1
338
        hread(L, gt1(base_width-1 downto 0), good_value);
339
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
340
 
341
      when 11 => -- gt01
342
        hread(L, gt01(base_width-1 downto 0), good_value);
343
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
344
 
345
        -- select pipeline for all computations
346
        ----------------------------------------
347
        writeline(output, Lw);
348
        write(Lw, string'("----- Selecting pipeline: "));
349
        writeline(output, Lw);
350
        case (base_width) is
351 43 JonasDC
          when C_NR_BITS_TOTAL =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
352
          when NR_BITS_HIGH =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
353
          when NR_BITS_LOW  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
354 2 JonasDC
          when others =>
355
            write(Lw, string'("  Invallid bitwidth for design"));
356
            assert false report "impossible basewidth!" severity failure;
357
        end case;
358
        writeline(output, Lw);
359
 
360
        writeline(output, Lw);
361
        write(Lw, string'("----- Writing operands:"));
362
        writeline(output, Lw);
363
 
364
        -- load the modulus
365
        --------------------
366
        loadOp(op_modulus, m); -- visual check needed
367
        write(Lw, string'("  m written"));
368
        writeline(output, Lw);
369
 
370
        -- load g0
371
        -----------
372
        loadOp(op_0, g0);
373
        -- verify
374
        readOp(op_0, data_read, base_width);
375
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
376
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
377
        else
378
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
379
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
380
        end if;
381
 
382
        -- load g1
383
        -----------
384
        loadOp(op_1, g1);
385
        -- verify
386
        readOp(op_1, data_read, base_width);
387
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
388
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
389
        else
390
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
391
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
392
        end if;
393
 
394
        -- load R2
395
        -----------
396
        loadOp(op_2, R2);
397
        -- verify
398
        readOp(op_2, data_read, base_width);
399
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
400
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
401
        else
402
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
403
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
404
        end if;
405
 
406
        -- load a=1
407
        ------------
408
        loadOp(op_3, one);
409
        -- verify
410
        readOp(op_3, data_read, base_width);
411
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
412
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
413
        else
414
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
415
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
416
        end if;
417
 
418
        writeline(output, Lw);
419
        write(Lw, string'("----- Pre-computations: "));
420
        writeline(output, Lw);
421
 
422
        -- compute gt0
423
        ---------------
424
        core_x_sel_single <= "00"; -- g0
425
        core_y_sel_single <= "10"; -- R^2
426
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
427
        wait until rising_edge(clk);
428
        timer := NOW;
429
        core_start <= '1';
430
        wait until rising_edge(clk);
431
        core_start <= '0';
432
        wait until core_ready = '1';
433
        timer := NOW-timer;
434
        waitclk(10);
435
        readOp(op_0, data_read, base_width);
436
        write(Lw, string'("  Computed gt0: "));
437
        hwrite(Lw, data_read(base_width-1 downto 0));
438
        writeline(output, Lw);
439
        write(Lw, string'("  Read gt0:     "));
440
        hwrite(Lw, gt0(base_width-1 downto 0));
441
        writeline(output, Lw);
442
        write(Lw, string'("  => calc time is "));
443
        write(Lw, string'(ToString(timer)));
444
        writeline(output, Lw);
445
        write(Lw, string'("  => expected time is "));
446 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
447 2 JonasDC
        writeline(output, Lw);
448
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
449
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
450
        else
451
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
452
          assert false report "gt0 is incorrect!!!" severity failure;
453
        end if;
454
 
455
        -- compute gt1
456
        ---------------
457
        core_x_sel_single <= "01"; -- g1
458
        core_y_sel_single <= "10"; -- R^2
459
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
460
        wait until rising_edge(clk);
461
        timer := NOW;
462
        core_start <= '1';
463
        wait until rising_edge(clk);
464
        core_start <= '0';
465
        wait until core_ready = '1';
466
        timer := NOW-timer;
467
        waitclk(10);
468
        readOp(op_1, data_read, base_width);
469
        write(Lw, string'("  Computed gt1: "));
470
        hwrite(Lw, data_read(base_width-1 downto 0));
471
        writeline(output, Lw);
472
        write(Lw, string'("  Read gt1:     "));
473
        hwrite(Lw, gt1(base_width-1 downto 0));
474
        writeline(output, Lw);
475
        write(Lw, string'("  => calc time is "));
476
        write(Lw, string'(ToString(timer)));
477
        writeline(output, Lw);
478
        write(Lw, string'("  => expected time is "));
479 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
480 2 JonasDC
        writeline(output, Lw);
481
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
482
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
483
        else
484
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
485
          assert false report "gt1 is incorrect!!!" severity failure;
486
        end if;
487
 
488
        -- compute a
489
        -------------
490
        core_x_sel_single <= "10"; -- R^2
491
        core_y_sel_single <= "11"; -- 1
492
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
493
        wait until rising_edge(clk);
494
        core_start <= '1';
495
        timer := NOW;
496
        wait until rising_edge(clk);
497
        core_start <= '0';
498
        wait until core_ready = '1';
499
        timer := NOW-timer;
500
        waitclk(10);
501
        readOp(op_3, data_read, base_width);
502
        write(Lw, string'("  Computed a=(R)mod m: "));
503
        hwrite(Lw, data_read(base_width-1 downto 0));
504
        writeline(output, Lw);
505
        write(Lw, string'("  Read (R)mod m:       "));
506
        hwrite(Lw, R(base_width-1 downto 0));
507
        writeline(output, Lw);
508
        write(Lw, string'("  => calc time is "));
509
        write(Lw, string'(ToString(timer)));
510
        writeline(output, Lw);
511
        write(Lw, string'("  => expected time is "));
512 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
513 2 JonasDC
        writeline(output, Lw);
514
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
515
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
516
        else
517
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
518
          assert false report "(R)mod m is incorrect!!!" severity failure;
519
        end if;
520
 
521
        -- compute gt01
522
        ---------------
523
        core_x_sel_single <= "00"; -- gt0
524
        core_y_sel_single <= "01"; -- gt1
525
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
526
        wait until rising_edge(clk);
527
        core_start <= '1';
528
        timer := NOW;
529
        wait until rising_edge(clk);
530
        core_start <= '0';
531
        wait until core_ready = '1';
532
        timer := NOW-timer;
533
        waitclk(10);
534
        readOp(op_2, data_read, base_width);
535
        write(Lw, string'("  Computed gt01: "));
536
        hwrite(Lw, data_read(base_width-1 downto 0));
537
        writeline(output, Lw);
538
        write(Lw, string'("  Read gt01:     "));
539
        hwrite(Lw, gt01(base_width-1 downto 0));
540
        writeline(output, Lw);
541
        write(Lw, string'("  => calc time is "));
542
        write(Lw, string'(ToString(timer)));
543
        writeline(output, Lw);
544
        write(Lw, string'("  => expected time is "));
545 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
546 2 JonasDC
        writeline(output, Lw);
547
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
548
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
549
        else
550
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
551
          assert false report "gt01 is incorrect!!!" severity failure;
552
        end if;
553
 
554
        -- load exponent fifo
555
        ----------------------
556
        writeline(output, Lw);
557
        write(Lw, string'("----- Loading exponent fifo: "));
558
        writeline(output, Lw);
559
        for i in (exponent_width/16)-1 downto 0 loop
560
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
561
          wait until rising_edge(clk);
562 70 JonasDC
          assert (core_fifo_full='0')
563
            report "Fifo error, fifo full" severity failure;
564 2 JonasDC
          core_fifo_push <= '1';
565
          wait until rising_edge(clk);
566
          assert (core_fifo_full='0' and core_fifo_nopush='0')
567 70 JonasDC
            report "Fifo error, fifo nopush" severity failure;
568 2 JonasDC
          core_fifo_push <= '0';
569
          wait until rising_edge(clk);
570
        end loop;
571
        waitclk(10);
572 3 JonasDC
        write(Lw, string'("  => Done"));
573 2 JonasDC
        writeline(output, Lw);
574
 
575
        -- start exponentiation
576
        ------------------------
577
        writeline(output, Lw);
578
        write(Lw, string'("----- Starting exponentiation: "));
579
        writeline(output, Lw);
580 46 JonasDC
        core_exp_m <= '1';
581 2 JonasDC
        wait until rising_edge(clk);
582
        timer := NOW;
583
        core_start <= '1';
584
        wait until rising_edge(clk);
585
        core_start <= '0';
586
        wait until core_ready='1';
587
        timer := NOW-timer;
588
        waitclk(10);
589
        write(Lw, string'("  => calc time is "));
590
        write(Lw, string'(ToString(timer)));
591
        writeline(output, Lw);
592
        write(Lw, string'("  => expected time is "));
593 43 JonasDC
        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
594 2 JonasDC
        writeline(output, Lw);
595
        write(Lw, string'("  => Done"));
596 46 JonasDC
        core_exp_m <= '0';
597 2 JonasDC
        writeline(output, Lw);
598
 
599
        -- post-computations
600
        ---------------------
601
        writeline(output, Lw);
602
        write(Lw, string'("----- Post-computations: "));
603
        writeline(output, Lw);
604
        -- load in 1 to operand 2
605
        loadOp(op_2, one);
606
        -- verify
607
        readOp(op_2, data_read, base_width);
608
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
609
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
610
        else
611
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
612
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
613
        end if;
614
        -- compute result
615
        core_x_sel_single <= "11"; -- a
616
        core_y_sel_single <= "10"; -- 1
617
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
618
        wait until rising_edge(clk);
619
        timer := NOW;
620
        core_start <= '1';
621
        wait until rising_edge(clk);
622
        core_start <= '0';
623
        wait until core_ready = '1';
624
        timer := NOW-timer;
625
        waitclk(10);
626
        readOp(op_3, data_read, base_width);
627
        write(Lw, string'("  Computed result: "));
628
        hwrite(Lw, data_read(base_width-1 downto 0));
629
        writeline(output, Lw);
630
        write(Lw, string'("  => calc time is "));
631
        write(Lw, string'(ToString(timer)));
632
        writeline(output, Lw);
633
        write(Lw, string'("  => expected time is "));
634 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
635 2 JonasDC
        writeline(output, Lw);
636
 
637
      when 12 => -- check with result
638
        hread(L, result(base_width-1 downto 0), good_value);
639
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
640
        writeline(output, Lw);
641
        write(Lw, string'("----- verifying result: "));
642
        writeline(output, Lw);
643
        write(Lw, string'("  Read result:     "));
644
        hwrite(Lw, result(base_width-1 downto 0));
645
        writeline(output, Lw);
646
        write(Lw, string'("  Computed result: "));
647
        hwrite(Lw, data_read(base_width-1 downto 0));
648
        writeline(output, Lw);
649
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
650
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
651
        else
652
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
653
          assert false report "result is incorrect!!!" severity failure;
654
        end if;
655
        writeline(output, Lw);
656
 
657
      when others =>
658
        assert false report "undefined state!" severity failure;
659
    end case;
660
 
661
    if (param_count = 12) then
662
      param_count := 0;
663
    else
664
      param_count := param_count+1;
665
    end if;
666
  end loop;
667
 
668
  wait for 1 us;
669
  assert false report "End of simulation" severity failure;
670
 
671
end process;
672
 
673
------------------------------------------
674
-- Multiplier core instance
675
------------------------------------------
676 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
677 43 JonasDC
generic map(
678
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
679
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
680
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
681 70 JonasDC
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
682
  C_NR_OP           => C_NR_OP,
683
  C_NR_M            => C_NR_M,
684
  C_FIFO_DEPTH      => C_FIFO_DEPTH,
685
  C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
686
  C_DEVICE          => C_DEVICE   -- xilinx, altera are valid options
687 43 JonasDC
)
688 2 JonasDC
port map(
689
  clk   => clk,
690
  reset => reset,
691
-- operand memory interface (plb shared memory)
692
  write_enable => core_write_enable,
693
  data_in      => core_data_in,
694
  rw_address   => core_rw_address,
695
  data_out     => core_data_out,
696
  collision    => core_mem_collision,
697
-- op_sel fifo interface
698
  fifo_din    => core_fifo_din,
699
  fifo_push   => core_fifo_push,
700
  fifo_full   => core_fifo_full,
701
  fifo_nopush => core_fifo_nopush,
702
-- ctrl signals
703
  start          => core_start,
704 46 JonasDC
  exp_m          => core_exp_m,
705 2 JonasDC
  ready          => core_ready,
706
  x_sel_single   => core_x_sel_single,
707
  y_sel_single   => core_y_sel_single,
708
  dest_op_single => core_dest_op_single,
709
  p_sel          => core_p_sel,
710 70 JonasDC
  calc_time      => calc_time,
711
  modulus_sel    => "0"
712 2 JonasDC
);
713
 
714
end test;

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