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1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 43 JonasDC
  constant CLK_PERIOD : time := 10 ns;
67 2 JonasDC
  signal clk          : std_logic := '0';
68
  signal reset        : std_logic := '1';
69 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
70
  file output         : text open write_mode is "out/sim_output.txt";
71 2 JonasDC
 
72
  ------------------------------------------------------------------
73 43 JonasDC
  -- Core parameters
74
  ------------------------------------------------------------------
75
  constant C_NR_BITS_TOTAL   : integer := 1536;
76
  constant C_NR_STAGES_TOTAL : integer := 96;
77
  constant C_NR_STAGES_LOW   : integer := 32;
78 70 JonasDC
  constant C_SPLIT_PIPELINE  : boolean := true;
79
  constant C_FIFO_DEPTH      : integer := 32; -- set to (maximum exponent width)/16
80 84 JonasDC
  constant C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
81
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
82 43 JonasDC
 
83
  -- extra calculated constants
84
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
85
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
86
 
87
  ------------------------------------------------------------------
88 2 JonasDC
  -- Signals for multiplier core memory space
89
  ------------------------------------------------------------------
90
  signal core_rw_address   : std_logic_vector (8 downto 0);
91
  signal core_data_in      : std_logic_vector(31 downto 0);
92
  signal core_fifo_din     : std_logic_vector(31 downto 0);
93
  signal core_data_out     : std_logic_vector(31 downto 0);
94
  signal core_write_enable : std_logic;
95
  signal core_fifo_push    : std_logic;
96
  ------------------------------------------------------------------
97
  -- Signals for multiplier core control
98
  ------------------------------------------------------------------
99
  signal core_start          : std_logic;
100 46 JonasDC
  signal core_exp_m          : std_logic;
101 2 JonasDC
  signal core_p_sel          : std_logic_vector(1 downto 0);
102
  signal core_dest_op_single : std_logic_vector(1 downto 0);
103
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
104
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
105
  signal calc_time           : std_logic;
106
  ------------------------------------------------------------------
107
  -- Signals for multiplier core interrupt
108
  ------------------------------------------------------------------
109
  signal core_fifo_full   : std_logic;
110
  signal core_fifo_nopush : std_logic;
111
  signal core_ready       : std_logic;
112
  signal core_mem_collision : std_logic;
113
 
114
begin
115
 
116
------------------------------------------
117
-- Generate clk
118
------------------------------------------
119
clk_process : process
120
begin
121
  while (true) loop
122
    clk <= '0';
123 43 JonasDC
    wait for CLK_PERIOD/2;
124 2 JonasDC
    clk <= '1';
125 43 JonasDC
    wait for CLK_PERIOD/2;
126 2 JonasDC
  end loop;
127
end process;
128
 
129
------------------------------------------
130
-- Stimulus Process
131
------------------------------------------
132
stim_proc : process
133
  procedure waitclk(n : natural := 1) is
134
  begin
135
    for i in 1 to n loop
136
      wait until rising_edge(clk);
137
    end loop;
138
  end waitclk;
139
 
140
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
141
               variable op_data : std_logic_vector(2047 downto 0)) is
142
  begin
143
    wait until rising_edge(clk);
144
    core_rw_address <= op_sel & "000000";
145
    wait until rising_edge(clk);
146
    core_write_enable <= '1';
147
    for i in 0 to (1536/32)-1 loop
148
      assert (core_mem_collision='0')
149
        report "collision detected while writing operand!!" severity failure;
150
      case (core_p_sel) is
151
        when "11" =>
152
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
153
        when "01" =>
154
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
155
          else core_data_in <= x"00000000"; end if;
156
        when "10" =>
157
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
158
          else core_data_in <= x"00000000"; end if;
159
        when others =>
160
          core_data_in <= x"00000000";
161
      end case;
162
 
163
      wait until rising_edge(clk);
164
      core_rw_address <= core_rw_address+"000000001";
165
    end loop;
166
    core_write_enable <= '0';
167
    wait until rising_edge(clk);
168
  end loadOp;
169
 
170
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
171
                  variable op_data  : out std_logic_vector(2047 downto 0);
172
                  variable op_width : integer) is
173
  begin
174
      wait until rising_edge(clk);
175
      core_dest_op_single <= op_sel(1 downto 0);
176
      if (core_p_sel = "10") then
177
        core_rw_address <= op_sel & "010000";
178
      else
179
        core_rw_address <= op_sel & "000000";
180
      end if;
181
      waitclk(2);
182
 
183
      for i in 0 to (op_width/32)-2 loop
184
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
185
          core_rw_address <= core_rw_address+"000000001";
186
          waitclk(2);
187
      end loop;
188
      op_data(op_width-1 downto op_width-32) := core_data_out;
189
      wait until rising_edge(clk);
190
  end readOp;
191
 
192
  function ToString(constant Timeval : time) return string is
193
    variable StrPtr : line;
194
  begin
195
    write(StrPtr,Timeval);
196
    return StrPtr.all;
197
  end ToString;
198
 
199
  -- variables to read file
200
  variable L : line;
201
  variable Lw : line;
202
  variable base_width : integer;
203
  variable exponent_width : integer;
204
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
205
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
206
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
207
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
208
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
209
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
210
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
211
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
212
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
213
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
214
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
215
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
216
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
217
  variable good_value : boolean;
218
  variable param_count : integer := 0;
219
 
220
  -- constants for operand selection
221
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
222
  constant op_0 : std_logic_vector(2 downto 0) := "000";
223
  constant op_1 : std_logic_vector(2 downto 0) := "001";
224
  constant op_2 : std_logic_vector(2 downto 0) := "010";
225
  constant op_3 : std_logic_vector(2 downto 0) := "011";
226
 
227
  variable timer : time;
228
begin
229
  -- initialisation
230
  -- memory
231
  core_write_enable <= '0';
232
  core_data_in <= x"00000000";
233
  core_rw_address <= "000000000";
234
  -- fifo
235
  core_fifo_din <= x"00000000";
236
  core_fifo_push <= '0';
237
  -- control
238
  core_start <= '0';
239 46 JonasDC
  core_exp_m <= '0';
240 2 JonasDC
  core_x_sel_single <= "00";
241
  core_y_sel_single <= "01";
242
  core_dest_op_single <= "01";
243
  core_p_sel <= "11";
244
 
245
  -- Generate active high reset signal
246
  reset <= '1';
247
  waitclk(100);
248
  reset <= '0';
249
  waitclk(100);
250
 
251
  while not endfile(input) loop
252
    readline(input, L); -- read next line
253
    next when L(1)='-'; -- skip comment lines
254
    -- read input values
255
    case param_count is
256
      when 0 => -- base width
257
        read(L, base_width, good_value);
258
        assert good_value report "Can not read base width" severity failure;
259
        assert false report "Simulating exponentiation" severity note;
260
        write(Lw, string'("----------------------------------------------"));
261
        writeline(output, Lw);
262
        write(Lw, string'("--              EXPONENTIATION              --"));
263
        writeline(output, Lw);
264
        write(Lw, string'("----------------------------------------------"));
265
        writeline(output, Lw);
266
        write(Lw, string'("----- Variables used:"));
267
        writeline(output, Lw);
268
        write(Lw, string'("base width: "));
269
        write(Lw, base_width);
270
        writeline(output, Lw);
271
        case (base_width) is
272 43 JonasDC
          when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
273 2 JonasDC
          when others =>
274
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
275
            assert false report "incompatible base width!!!" severity failure;
276
        end case;
277
 
278
      when 1 => -- exponent width
279
        read(L, exponent_width, good_value);
280
        assert good_value report "Can not read exponent width" severity failure;
281
        write(Lw, string'("exponent width: "));
282
        write(Lw, exponent_width);
283
        writeline(output, Lw);
284
 
285
      when 2 => -- g0
286
        hread(L, g0(base_width-1 downto 0), good_value);
287
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
288
        write(Lw, string'("g0: "));
289
        hwrite(Lw, g0(base_width-1 downto 0));
290
        writeline(output, Lw);
291
 
292
      when 3 => -- g1
293
        hread(L, g1(base_width-1 downto 0), good_value);
294
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
295
        write(Lw, string'("g1: "));
296
        hwrite(Lw, g1(base_width-1 downto 0));
297
        writeline(output, Lw);
298
 
299
      when 4 => -- e0
300
        hread(L, e0(exponent_width-1 downto 0), good_value);
301
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
302
        write(Lw, string'("e0: "));
303
        hwrite(Lw, e0(exponent_width-1 downto 0));
304
        writeline(output, Lw);
305
 
306
      when 5 => -- e1
307
        hread(L, e1(exponent_width-1 downto 0), good_value);
308
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
309
        write(Lw, string'("e1: "));
310
        hwrite(Lw, e1(exponent_width-1 downto 0));
311
        writeline(output, Lw);
312
 
313
      when 6 => -- m
314
        hread(L, m(base_width-1 downto 0), good_value);
315
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
316
        write(Lw, string'("m:  "));
317
        hwrite(Lw, m(base_width-1 downto 0));
318
        writeline(output, Lw);
319
 
320
      when 7 => -- R^2
321
        hread(L, R2(base_width-1 downto 0), good_value);
322
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
323
        write(Lw, string'("R2: "));
324
        hwrite(Lw, R2(base_width-1 downto 0));
325
        writeline(output, Lw);
326
 
327
      when 8 => -- R
328
        hread(L, R(base_width-1 downto 0), good_value);
329
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
330
 
331
      when 9 => -- gt0
332
        hread(L, gt0(base_width-1 downto 0), good_value);
333
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
334
 
335
      when 10 => -- gt1
336
        hread(L, gt1(base_width-1 downto 0), good_value);
337
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
338
 
339
      when 11 => -- gt01
340
        hread(L, gt01(base_width-1 downto 0), good_value);
341
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
342
 
343
        -- select pipeline for all computations
344
        ----------------------------------------
345
        writeline(output, Lw);
346
        write(Lw, string'("----- Selecting pipeline: "));
347
        writeline(output, Lw);
348
        case (base_width) is
349 43 JonasDC
          when C_NR_BITS_TOTAL =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
350
          when NR_BITS_HIGH =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
351
          when NR_BITS_LOW  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
352 2 JonasDC
          when others =>
353
            write(Lw, string'("  Invallid bitwidth for design"));
354
            assert false report "impossible basewidth!" severity failure;
355
        end case;
356
        writeline(output, Lw);
357
 
358
        writeline(output, Lw);
359
        write(Lw, string'("----- Writing operands:"));
360
        writeline(output, Lw);
361
 
362
        -- load the modulus
363
        --------------------
364
        loadOp(op_modulus, m); -- visual check needed
365
        write(Lw, string'("  m written"));
366
        writeline(output, Lw);
367
 
368
        -- load g0
369
        -----------
370
        loadOp(op_0, g0);
371
        -- verify
372
        readOp(op_0, data_read, base_width);
373
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
374
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
375
        else
376
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
377
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
378
        end if;
379
 
380
        -- load g1
381
        -----------
382
        loadOp(op_1, g1);
383
        -- verify
384
        readOp(op_1, data_read, base_width);
385
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
386
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
387
        else
388
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
389
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
390
        end if;
391
 
392
        -- load R2
393
        -----------
394
        loadOp(op_2, R2);
395
        -- verify
396
        readOp(op_2, data_read, base_width);
397
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
398
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
399
        else
400
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
401
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
402
        end if;
403
 
404
        -- load a=1
405
        ------------
406
        loadOp(op_3, one);
407
        -- verify
408
        readOp(op_3, data_read, base_width);
409
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
410
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
411
        else
412
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
413
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
414
        end if;
415
 
416
        writeline(output, Lw);
417
        write(Lw, string'("----- Pre-computations: "));
418
        writeline(output, Lw);
419
 
420
        -- compute gt0
421
        ---------------
422
        core_x_sel_single <= "00"; -- g0
423
        core_y_sel_single <= "10"; -- R^2
424
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
425
        wait until rising_edge(clk);
426
        timer := NOW;
427
        core_start <= '1';
428
        wait until rising_edge(clk);
429
        core_start <= '0';
430
        wait until core_ready = '1';
431
        timer := NOW-timer;
432
        waitclk(10);
433
        readOp(op_0, data_read, base_width);
434
        write(Lw, string'("  Computed gt0: "));
435
        hwrite(Lw, data_read(base_width-1 downto 0));
436
        writeline(output, Lw);
437
        write(Lw, string'("  Read gt0:     "));
438
        hwrite(Lw, gt0(base_width-1 downto 0));
439
        writeline(output, Lw);
440
        write(Lw, string'("  => calc time is "));
441
        write(Lw, string'(ToString(timer)));
442
        writeline(output, Lw);
443
        write(Lw, string'("  => expected time is "));
444 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
445 2 JonasDC
        writeline(output, Lw);
446
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
447
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
448
        else
449
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
450
          assert false report "gt0 is incorrect!!!" severity failure;
451
        end if;
452
 
453
        -- compute gt1
454
        ---------------
455
        core_x_sel_single <= "01"; -- g1
456
        core_y_sel_single <= "10"; -- R^2
457
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
458
        wait until rising_edge(clk);
459
        timer := NOW;
460
        core_start <= '1';
461
        wait until rising_edge(clk);
462
        core_start <= '0';
463
        wait until core_ready = '1';
464
        timer := NOW-timer;
465
        waitclk(10);
466
        readOp(op_1, data_read, base_width);
467
        write(Lw, string'("  Computed gt1: "));
468
        hwrite(Lw, data_read(base_width-1 downto 0));
469
        writeline(output, Lw);
470
        write(Lw, string'("  Read gt1:     "));
471
        hwrite(Lw, gt1(base_width-1 downto 0));
472
        writeline(output, Lw);
473
        write(Lw, string'("  => calc time is "));
474
        write(Lw, string'(ToString(timer)));
475
        writeline(output, Lw);
476
        write(Lw, string'("  => expected time is "));
477 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
478 2 JonasDC
        writeline(output, Lw);
479
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
480
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
481
        else
482
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
483
          assert false report "gt1 is incorrect!!!" severity failure;
484
        end if;
485
 
486
        -- compute a
487
        -------------
488
        core_x_sel_single <= "10"; -- R^2
489
        core_y_sel_single <= "11"; -- 1
490
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
491
        wait until rising_edge(clk);
492
        core_start <= '1';
493
        timer := NOW;
494
        wait until rising_edge(clk);
495
        core_start <= '0';
496
        wait until core_ready = '1';
497
        timer := NOW-timer;
498
        waitclk(10);
499
        readOp(op_3, data_read, base_width);
500
        write(Lw, string'("  Computed a=(R)mod m: "));
501
        hwrite(Lw, data_read(base_width-1 downto 0));
502
        writeline(output, Lw);
503
        write(Lw, string'("  Read (R)mod m:       "));
504
        hwrite(Lw, R(base_width-1 downto 0));
505
        writeline(output, Lw);
506
        write(Lw, string'("  => calc time is "));
507
        write(Lw, string'(ToString(timer)));
508
        writeline(output, Lw);
509
        write(Lw, string'("  => expected time is "));
510 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
511 2 JonasDC
        writeline(output, Lw);
512
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
513
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
514
        else
515
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
516
          assert false report "(R)mod m is incorrect!!!" severity failure;
517
        end if;
518
 
519
        -- compute gt01
520
        ---------------
521
        core_x_sel_single <= "00"; -- gt0
522
        core_y_sel_single <= "01"; -- gt1
523
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
524
        wait until rising_edge(clk);
525
        core_start <= '1';
526
        timer := NOW;
527
        wait until rising_edge(clk);
528
        core_start <= '0';
529
        wait until core_ready = '1';
530
        timer := NOW-timer;
531
        waitclk(10);
532
        readOp(op_2, data_read, base_width);
533
        write(Lw, string'("  Computed gt01: "));
534
        hwrite(Lw, data_read(base_width-1 downto 0));
535
        writeline(output, Lw);
536
        write(Lw, string'("  Read gt01:     "));
537
        hwrite(Lw, gt01(base_width-1 downto 0));
538
        writeline(output, Lw);
539
        write(Lw, string'("  => calc time is "));
540
        write(Lw, string'(ToString(timer)));
541
        writeline(output, Lw);
542
        write(Lw, string'("  => expected time is "));
543 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
544 2 JonasDC
        writeline(output, Lw);
545
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
546
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
547
        else
548
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
549
          assert false report "gt01 is incorrect!!!" severity failure;
550
        end if;
551
 
552
        -- load exponent fifo
553
        ----------------------
554
        writeline(output, Lw);
555
        write(Lw, string'("----- Loading exponent fifo: "));
556
        writeline(output, Lw);
557
        for i in (exponent_width/16)-1 downto 0 loop
558
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
559
          wait until rising_edge(clk);
560 70 JonasDC
          assert (core_fifo_full='0')
561
            report "Fifo error, fifo full" severity failure;
562 2 JonasDC
          core_fifo_push <= '1';
563
          wait until rising_edge(clk);
564
          assert (core_fifo_full='0' and core_fifo_nopush='0')
565 70 JonasDC
            report "Fifo error, fifo nopush" severity failure;
566 2 JonasDC
          core_fifo_push <= '0';
567
          wait until rising_edge(clk);
568
        end loop;
569
        waitclk(10);
570 3 JonasDC
        write(Lw, string'("  => Done"));
571 2 JonasDC
        writeline(output, Lw);
572
 
573
        -- start exponentiation
574
        ------------------------
575
        writeline(output, Lw);
576
        write(Lw, string'("----- Starting exponentiation: "));
577
        writeline(output, Lw);
578 46 JonasDC
        core_exp_m <= '1';
579 2 JonasDC
        wait until rising_edge(clk);
580
        timer := NOW;
581
        core_start <= '1';
582
        wait until rising_edge(clk);
583
        core_start <= '0';
584
        wait until core_ready='1';
585
        timer := NOW-timer;
586
        waitclk(10);
587
        write(Lw, string'("  => calc time is "));
588
        write(Lw, string'(ToString(timer)));
589
        writeline(output, Lw);
590
        write(Lw, string'("  => expected time is "));
591 43 JonasDC
        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
592 2 JonasDC
        writeline(output, Lw);
593
        write(Lw, string'("  => Done"));
594 46 JonasDC
        core_exp_m <= '0';
595 2 JonasDC
        writeline(output, Lw);
596
 
597
        -- post-computations
598
        ---------------------
599
        writeline(output, Lw);
600
        write(Lw, string'("----- Post-computations: "));
601
        writeline(output, Lw);
602
        -- load in 1 to operand 2
603
        loadOp(op_2, one);
604
        -- verify
605
        readOp(op_2, data_read, base_width);
606
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
607
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
608
        else
609
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
610
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
611
        end if;
612
        -- compute result
613
        core_x_sel_single <= "11"; -- a
614
        core_y_sel_single <= "10"; -- 1
615
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
616
        wait until rising_edge(clk);
617
        timer := NOW;
618
        core_start <= '1';
619
        wait until rising_edge(clk);
620
        core_start <= '0';
621
        wait until core_ready = '1';
622
        timer := NOW-timer;
623
        waitclk(10);
624
        readOp(op_3, data_read, base_width);
625
        write(Lw, string'("  Computed result: "));
626
        hwrite(Lw, data_read(base_width-1 downto 0));
627
        writeline(output, Lw);
628
        write(Lw, string'("  => calc time is "));
629
        write(Lw, string'(ToString(timer)));
630
        writeline(output, Lw);
631
        write(Lw, string'("  => expected time is "));
632 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
633 2 JonasDC
        writeline(output, Lw);
634
 
635
      when 12 => -- check with result
636
        hread(L, result(base_width-1 downto 0), good_value);
637
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
638
        writeline(output, Lw);
639
        write(Lw, string'("----- verifying result: "));
640
        writeline(output, Lw);
641
        write(Lw, string'("  Read result:     "));
642
        hwrite(Lw, result(base_width-1 downto 0));
643
        writeline(output, Lw);
644
        write(Lw, string'("  Computed result: "));
645
        hwrite(Lw, data_read(base_width-1 downto 0));
646
        writeline(output, Lw);
647
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
648
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
649
        else
650
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
651
          assert false report "result is incorrect!!!" severity failure;
652
        end if;
653
        writeline(output, Lw);
654
 
655
      when others =>
656
        assert false report "undefined state!" severity failure;
657
    end case;
658
 
659
    if (param_count = 12) then
660
      param_count := 0;
661
    else
662
      param_count := param_count+1;
663
    end if;
664
  end loop;
665
 
666
  wait for 1 us;
667
  assert false report "End of simulation" severity failure;
668
 
669
end process;
670
 
671
------------------------------------------
672
-- Multiplier core instance
673
------------------------------------------
674 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
675 43 JonasDC
generic map(
676
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
677
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
678
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
679 70 JonasDC
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
680
  C_FIFO_DEPTH      => C_FIFO_DEPTH,
681
  C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
682 84 JonasDC
  C_FPGA_MAN        => C_FPGA_MAN   -- xilinx, altera are valid options
683 43 JonasDC
)
684 2 JonasDC
port map(
685
  clk   => clk,
686
  reset => reset,
687
-- operand memory interface (plb shared memory)
688
  write_enable => core_write_enable,
689
  data_in      => core_data_in,
690
  rw_address   => core_rw_address,
691
  data_out     => core_data_out,
692
  collision    => core_mem_collision,
693
-- op_sel fifo interface
694
  fifo_din    => core_fifo_din,
695
  fifo_push   => core_fifo_push,
696
  fifo_full   => core_fifo_full,
697
  fifo_nopush => core_fifo_nopush,
698
-- ctrl signals
699
  start          => core_start,
700 46 JonasDC
  exp_m          => core_exp_m,
701 2 JonasDC
  ready          => core_ready,
702
  x_sel_single   => core_x_sel_single,
703
  y_sel_single   => core_y_sel_single,
704
  dest_op_single => core_dest_op_single,
705
  p_sel          => core_p_sel,
706 70 JonasDC
  calc_time      => calc_time,
707 84 JonasDC
  modulus_sel    => '0'
708 2 JonasDC
);
709
 
710
end test;

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