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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Blame information for rev 94

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1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 43 JonasDC
  constant CLK_PERIOD : time := 10 ns;
67 2 JonasDC
  signal clk          : std_logic := '0';
68 94 JonasDC
  constant CORE_CLK_PERIOD : time := 4 ns;
69
  signal core_clk     : std_logic := '0';
70 2 JonasDC
  signal reset        : std_logic := '1';
71 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
72
  file output         : text open write_mode is "out/sim_output.txt";
73 2 JonasDC
 
74
  ------------------------------------------------------------------
75 43 JonasDC
  -- Core parameters
76
  ------------------------------------------------------------------
77
  constant C_NR_BITS_TOTAL   : integer := 1536;
78
  constant C_NR_STAGES_TOTAL : integer := 96;
79
  constant C_NR_STAGES_LOW   : integer := 32;
80 70 JonasDC
  constant C_SPLIT_PIPELINE  : boolean := true;
81 94 JonasDC
  constant C_FIFO_AW         : integer := 7; -- set to log2( (maximum exponent width)/16 )
82 84 JonasDC
  constant C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
83
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
84 43 JonasDC
 
85
  -- extra calculated constants
86
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
87
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
88
 
89
  ------------------------------------------------------------------
90 2 JonasDC
  -- Signals for multiplier core memory space
91
  ------------------------------------------------------------------
92
  signal core_rw_address   : std_logic_vector (8 downto 0);
93
  signal core_data_in      : std_logic_vector(31 downto 0);
94
  signal core_fifo_din     : std_logic_vector(31 downto 0);
95
  signal core_data_out     : std_logic_vector(31 downto 0);
96
  signal core_write_enable : std_logic;
97
  signal core_fifo_push    : std_logic;
98
  ------------------------------------------------------------------
99
  -- Signals for multiplier core control
100
  ------------------------------------------------------------------
101
  signal core_start          : std_logic;
102 46 JonasDC
  signal core_exp_m          : std_logic;
103 2 JonasDC
  signal core_p_sel          : std_logic_vector(1 downto 0);
104
  signal core_dest_op_single : std_logic_vector(1 downto 0);
105
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
106
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
107
  signal calc_time           : std_logic;
108
  ------------------------------------------------------------------
109
  -- Signals for multiplier core interrupt
110
  ------------------------------------------------------------------
111
  signal core_fifo_full   : std_logic;
112
  signal core_fifo_nopush : std_logic;
113
  signal core_ready       : std_logic;
114
  signal core_mem_collision : std_logic;
115
 
116
begin
117
 
118
------------------------------------------
119
-- Generate clk
120
------------------------------------------
121
clk_process : process
122
begin
123
  while (true) loop
124
    clk <= '0';
125 43 JonasDC
    wait for CLK_PERIOD/2;
126 2 JonasDC
    clk <= '1';
127 43 JonasDC
    wait for CLK_PERIOD/2;
128 2 JonasDC
  end loop;
129
end process;
130
 
131 94 JonasDC
core_clk_process : process
132
begin
133
  while (true) loop
134
    core_clk <= '0';
135
    wait for CORE_CLK_PERIOD/2;
136
    core_clk <= '1';
137
    wait for CORE_CLK_PERIOD/2;
138
  end loop;
139
end process;
140
 
141 2 JonasDC
------------------------------------------
142
-- Stimulus Process
143
------------------------------------------
144
stim_proc : process
145
  procedure waitclk(n : natural := 1) is
146
  begin
147
    for i in 1 to n loop
148
      wait until rising_edge(clk);
149
    end loop;
150
  end waitclk;
151
 
152
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
153
               variable op_data : std_logic_vector(2047 downto 0)) is
154
  begin
155
    wait until rising_edge(clk);
156
    core_rw_address <= op_sel & "000000";
157
    wait until rising_edge(clk);
158
    core_write_enable <= '1';
159
    for i in 0 to (1536/32)-1 loop
160
      assert (core_mem_collision='0')
161
        report "collision detected while writing operand!!" severity failure;
162
      case (core_p_sel) is
163
        when "11" =>
164
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
165
        when "01" =>
166
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
167
          else core_data_in <= x"00000000"; end if;
168
        when "10" =>
169
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
170
          else core_data_in <= x"00000000"; end if;
171
        when others =>
172
          core_data_in <= x"00000000";
173
      end case;
174
 
175
      wait until rising_edge(clk);
176
      core_rw_address <= core_rw_address+"000000001";
177
    end loop;
178
    core_write_enable <= '0';
179
    wait until rising_edge(clk);
180
  end loadOp;
181
 
182
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
183
                  variable op_data  : out std_logic_vector(2047 downto 0);
184
                  variable op_width : integer) is
185
  begin
186
      wait until rising_edge(clk);
187
      core_dest_op_single <= op_sel(1 downto 0);
188
      if (core_p_sel = "10") then
189
        core_rw_address <= op_sel & "010000";
190
      else
191
        core_rw_address <= op_sel & "000000";
192
      end if;
193
      waitclk(2);
194
 
195
      for i in 0 to (op_width/32)-2 loop
196
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
197
          core_rw_address <= core_rw_address+"000000001";
198
          waitclk(2);
199
      end loop;
200
      op_data(op_width-1 downto op_width-32) := core_data_out;
201
      wait until rising_edge(clk);
202
  end readOp;
203
 
204
  function ToString(constant Timeval : time) return string is
205
    variable StrPtr : line;
206
  begin
207
    write(StrPtr,Timeval);
208
    return StrPtr.all;
209
  end ToString;
210
 
211
  -- variables to read file
212
  variable L : line;
213
  variable Lw : line;
214
  variable base_width : integer;
215
  variable exponent_width : integer;
216
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
217
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
218
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
219
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
220
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
221
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
222
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
223
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
224
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
225
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
226
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
227
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
228
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
229
  variable good_value : boolean;
230
  variable param_count : integer := 0;
231
 
232
  -- constants for operand selection
233
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
234
  constant op_0 : std_logic_vector(2 downto 0) := "000";
235
  constant op_1 : std_logic_vector(2 downto 0) := "001";
236
  constant op_2 : std_logic_vector(2 downto 0) := "010";
237
  constant op_3 : std_logic_vector(2 downto 0) := "011";
238
 
239
  variable timer : time;
240
begin
241
  -- initialisation
242
  -- memory
243
  core_write_enable <= '0';
244
  core_data_in <= x"00000000";
245
  core_rw_address <= "000000000";
246
  -- fifo
247
  core_fifo_din <= x"00000000";
248
  core_fifo_push <= '0';
249
  -- control
250
  core_start <= '0';
251 46 JonasDC
  core_exp_m <= '0';
252 2 JonasDC
  core_x_sel_single <= "00";
253
  core_y_sel_single <= "01";
254
  core_dest_op_single <= "01";
255
  core_p_sel <= "11";
256
 
257
  -- Generate active high reset signal
258
  reset <= '1';
259
  waitclk(100);
260
  reset <= '0';
261
  waitclk(100);
262
 
263
  while not endfile(input) loop
264
    readline(input, L); -- read next line
265
    next when L(1)='-'; -- skip comment lines
266
    -- read input values
267
    case param_count is
268
      when 0 => -- base width
269
        read(L, base_width, good_value);
270
        assert good_value report "Can not read base width" severity failure;
271
        assert false report "Simulating exponentiation" severity note;
272
        write(Lw, string'("----------------------------------------------"));
273
        writeline(output, Lw);
274
        write(Lw, string'("--              EXPONENTIATION              --"));
275
        writeline(output, Lw);
276
        write(Lw, string'("----------------------------------------------"));
277
        writeline(output, Lw);
278
        write(Lw, string'("----- Variables used:"));
279
        writeline(output, Lw);
280
        write(Lw, string'("base width: "));
281
        write(Lw, base_width);
282
        writeline(output, Lw);
283
        case (base_width) is
284 43 JonasDC
          when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
285 2 JonasDC
          when others =>
286
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
287
            assert false report "incompatible base width!!!" severity failure;
288
        end case;
289
 
290
      when 1 => -- exponent width
291
        read(L, exponent_width, good_value);
292
        assert good_value report "Can not read exponent width" severity failure;
293
        write(Lw, string'("exponent width: "));
294
        write(Lw, exponent_width);
295
        writeline(output, Lw);
296
 
297
      when 2 => -- g0
298
        hread(L, g0(base_width-1 downto 0), good_value);
299
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
300
        write(Lw, string'("g0: "));
301
        hwrite(Lw, g0(base_width-1 downto 0));
302
        writeline(output, Lw);
303
 
304
      when 3 => -- g1
305
        hread(L, g1(base_width-1 downto 0), good_value);
306
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
307
        write(Lw, string'("g1: "));
308
        hwrite(Lw, g1(base_width-1 downto 0));
309
        writeline(output, Lw);
310
 
311
      when 4 => -- e0
312
        hread(L, e0(exponent_width-1 downto 0), good_value);
313
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
314
        write(Lw, string'("e0: "));
315
        hwrite(Lw, e0(exponent_width-1 downto 0));
316
        writeline(output, Lw);
317
 
318
      when 5 => -- e1
319
        hread(L, e1(exponent_width-1 downto 0), good_value);
320
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
321
        write(Lw, string'("e1: "));
322
        hwrite(Lw, e1(exponent_width-1 downto 0));
323
        writeline(output, Lw);
324
 
325
      when 6 => -- m
326
        hread(L, m(base_width-1 downto 0), good_value);
327
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
328
        write(Lw, string'("m:  "));
329
        hwrite(Lw, m(base_width-1 downto 0));
330
        writeline(output, Lw);
331
 
332
      when 7 => -- R^2
333
        hread(L, R2(base_width-1 downto 0), good_value);
334
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
335
        write(Lw, string'("R2: "));
336
        hwrite(Lw, R2(base_width-1 downto 0));
337
        writeline(output, Lw);
338
 
339
      when 8 => -- R
340
        hread(L, R(base_width-1 downto 0), good_value);
341
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
342
 
343
      when 9 => -- gt0
344
        hread(L, gt0(base_width-1 downto 0), good_value);
345
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
346
 
347
      when 10 => -- gt1
348
        hread(L, gt1(base_width-1 downto 0), good_value);
349
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
350
 
351
      when 11 => -- gt01
352
        hread(L, gt01(base_width-1 downto 0), good_value);
353
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
354
 
355
        -- select pipeline for all computations
356
        ----------------------------------------
357
        writeline(output, Lw);
358
        write(Lw, string'("----- Selecting pipeline: "));
359
        writeline(output, Lw);
360
        case (base_width) is
361 43 JonasDC
          when C_NR_BITS_TOTAL =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
362
          when NR_BITS_HIGH =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
363
          when NR_BITS_LOW  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
364 2 JonasDC
          when others =>
365
            write(Lw, string'("  Invallid bitwidth for design"));
366
            assert false report "impossible basewidth!" severity failure;
367
        end case;
368
        writeline(output, Lw);
369
 
370
        writeline(output, Lw);
371
        write(Lw, string'("----- Writing operands:"));
372
        writeline(output, Lw);
373
 
374
        -- load the modulus
375
        --------------------
376
        loadOp(op_modulus, m); -- visual check needed
377
        write(Lw, string'("  m written"));
378
        writeline(output, Lw);
379
 
380
        -- load g0
381
        -----------
382
        loadOp(op_0, g0);
383
        -- verify
384
        readOp(op_0, data_read, base_width);
385
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
386
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
387
        else
388
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
389
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
390
        end if;
391
 
392
        -- load g1
393
        -----------
394
        loadOp(op_1, g1);
395
        -- verify
396
        readOp(op_1, data_read, base_width);
397
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
398
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
399
        else
400
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
401
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
402
        end if;
403
 
404
        -- load R2
405
        -----------
406
        loadOp(op_2, R2);
407
        -- verify
408
        readOp(op_2, data_read, base_width);
409
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
410
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
411
        else
412
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
413
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
414
        end if;
415
 
416
        -- load a=1
417
        ------------
418
        loadOp(op_3, one);
419
        -- verify
420
        readOp(op_3, data_read, base_width);
421
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
422
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
423
        else
424
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
425
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
426
        end if;
427
 
428
        writeline(output, Lw);
429
        write(Lw, string'("----- Pre-computations: "));
430
        writeline(output, Lw);
431
 
432
        -- compute gt0
433
        ---------------
434
        core_x_sel_single <= "00"; -- g0
435
        core_y_sel_single <= "10"; -- R^2
436
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
437
        wait until rising_edge(clk);
438
        timer := NOW;
439
        core_start <= '1';
440
        wait until rising_edge(clk);
441
        core_start <= '0';
442
        wait until core_ready = '1';
443
        timer := NOW-timer;
444
        waitclk(10);
445
        readOp(op_0, data_read, base_width);
446
        write(Lw, string'("  Computed gt0: "));
447
        hwrite(Lw, data_read(base_width-1 downto 0));
448
        writeline(output, Lw);
449
        write(Lw, string'("  Read gt0:     "));
450
        hwrite(Lw, gt0(base_width-1 downto 0));
451
        writeline(output, Lw);
452
        write(Lw, string'("  => calc time is "));
453
        write(Lw, string'(ToString(timer)));
454
        writeline(output, Lw);
455
        write(Lw, string'("  => expected time is "));
456 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
457 2 JonasDC
        writeline(output, Lw);
458
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
459
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
460
        else
461
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
462
          assert false report "gt0 is incorrect!!!" severity failure;
463
        end if;
464
 
465
        -- compute gt1
466
        ---------------
467
        core_x_sel_single <= "01"; -- g1
468
        core_y_sel_single <= "10"; -- R^2
469
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
470
        wait until rising_edge(clk);
471
        timer := NOW;
472
        core_start <= '1';
473
        wait until rising_edge(clk);
474
        core_start <= '0';
475
        wait until core_ready = '1';
476
        timer := NOW-timer;
477
        waitclk(10);
478
        readOp(op_1, data_read, base_width);
479
        write(Lw, string'("  Computed gt1: "));
480
        hwrite(Lw, data_read(base_width-1 downto 0));
481
        writeline(output, Lw);
482
        write(Lw, string'("  Read gt1:     "));
483
        hwrite(Lw, gt1(base_width-1 downto 0));
484
        writeline(output, Lw);
485
        write(Lw, string'("  => calc time is "));
486
        write(Lw, string'(ToString(timer)));
487
        writeline(output, Lw);
488
        write(Lw, string'("  => expected time is "));
489 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
490 2 JonasDC
        writeline(output, Lw);
491
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
492
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
493
        else
494
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
495
          assert false report "gt1 is incorrect!!!" severity failure;
496
        end if;
497
 
498
        -- compute a
499
        -------------
500
        core_x_sel_single <= "10"; -- R^2
501
        core_y_sel_single <= "11"; -- 1
502
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
503
        wait until rising_edge(clk);
504
        core_start <= '1';
505
        timer := NOW;
506
        wait until rising_edge(clk);
507
        core_start <= '0';
508
        wait until core_ready = '1';
509
        timer := NOW-timer;
510
        waitclk(10);
511
        readOp(op_3, data_read, base_width);
512
        write(Lw, string'("  Computed a=(R)mod m: "));
513
        hwrite(Lw, data_read(base_width-1 downto 0));
514
        writeline(output, Lw);
515
        write(Lw, string'("  Read (R)mod m:       "));
516
        hwrite(Lw, R(base_width-1 downto 0));
517
        writeline(output, Lw);
518
        write(Lw, string'("  => calc time is "));
519
        write(Lw, string'(ToString(timer)));
520
        writeline(output, Lw);
521
        write(Lw, string'("  => expected time is "));
522 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
523 2 JonasDC
        writeline(output, Lw);
524
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
525
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
526
        else
527
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
528
          assert false report "(R)mod m is incorrect!!!" severity failure;
529
        end if;
530
 
531
        -- compute gt01
532
        ---------------
533
        core_x_sel_single <= "00"; -- gt0
534
        core_y_sel_single <= "01"; -- gt1
535
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
536
        wait until rising_edge(clk);
537
        core_start <= '1';
538
        timer := NOW;
539
        wait until rising_edge(clk);
540
        core_start <= '0';
541
        wait until core_ready = '1';
542
        timer := NOW-timer;
543
        waitclk(10);
544
        readOp(op_2, data_read, base_width);
545
        write(Lw, string'("  Computed gt01: "));
546
        hwrite(Lw, data_read(base_width-1 downto 0));
547
        writeline(output, Lw);
548
        write(Lw, string'("  Read gt01:     "));
549
        hwrite(Lw, gt01(base_width-1 downto 0));
550
        writeline(output, Lw);
551
        write(Lw, string'("  => calc time is "));
552
        write(Lw, string'(ToString(timer)));
553
        writeline(output, Lw);
554
        write(Lw, string'("  => expected time is "));
555 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
556 2 JonasDC
        writeline(output, Lw);
557
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
558
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
559
        else
560
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
561
          assert false report "gt01 is incorrect!!!" severity failure;
562
        end if;
563
 
564
        -- load exponent fifo
565
        ----------------------
566
        writeline(output, Lw);
567
        write(Lw, string'("----- Loading exponent fifo: "));
568
        writeline(output, Lw);
569
        for i in (exponent_width/16)-1 downto 0 loop
570
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
571
          wait until rising_edge(clk);
572 70 JonasDC
          assert (core_fifo_full='0')
573
            report "Fifo error, fifo full" severity failure;
574 2 JonasDC
          core_fifo_push <= '1';
575
          wait until rising_edge(clk);
576
          assert (core_fifo_full='0' and core_fifo_nopush='0')
577 70 JonasDC
            report "Fifo error, fifo nopush" severity failure;
578 2 JonasDC
          core_fifo_push <= '0';
579
          wait until rising_edge(clk);
580
        end loop;
581
        waitclk(10);
582 3 JonasDC
        write(Lw, string'("  => Done"));
583 2 JonasDC
        writeline(output, Lw);
584
 
585
        -- start exponentiation
586
        ------------------------
587
        writeline(output, Lw);
588
        write(Lw, string'("----- Starting exponentiation: "));
589
        writeline(output, Lw);
590 46 JonasDC
        core_exp_m <= '1';
591 2 JonasDC
        wait until rising_edge(clk);
592
        timer := NOW;
593
        core_start <= '1';
594
        wait until rising_edge(clk);
595
        core_start <= '0';
596
        wait until core_ready='1';
597
        timer := NOW-timer;
598
        waitclk(10);
599
        write(Lw, string'("  => calc time is "));
600
        write(Lw, string'(ToString(timer)));
601
        writeline(output, Lw);
602
        write(Lw, string'("  => expected time is "));
603 43 JonasDC
        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
604 2 JonasDC
        writeline(output, Lw);
605
        write(Lw, string'("  => Done"));
606 46 JonasDC
        core_exp_m <= '0';
607 2 JonasDC
        writeline(output, Lw);
608
 
609
        -- post-computations
610
        ---------------------
611
        writeline(output, Lw);
612
        write(Lw, string'("----- Post-computations: "));
613
        writeline(output, Lw);
614
        -- load in 1 to operand 2
615
        loadOp(op_2, one);
616
        -- verify
617
        readOp(op_2, data_read, base_width);
618
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
619
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
620
        else
621
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
622
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
623
        end if;
624
        -- compute result
625
        core_x_sel_single <= "11"; -- a
626
        core_y_sel_single <= "10"; -- 1
627
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
628
        wait until rising_edge(clk);
629
        timer := NOW;
630
        core_start <= '1';
631
        wait until rising_edge(clk);
632
        core_start <= '0';
633
        wait until core_ready = '1';
634
        timer := NOW-timer;
635
        waitclk(10);
636
        readOp(op_3, data_read, base_width);
637
        write(Lw, string'("  Computed result: "));
638
        hwrite(Lw, data_read(base_width-1 downto 0));
639
        writeline(output, Lw);
640
        write(Lw, string'("  => calc time is "));
641
        write(Lw, string'(ToString(timer)));
642
        writeline(output, Lw);
643
        write(Lw, string'("  => expected time is "));
644 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
645 2 JonasDC
        writeline(output, Lw);
646
 
647
      when 12 => -- check with result
648
        hread(L, result(base_width-1 downto 0), good_value);
649
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
650
        writeline(output, Lw);
651
        write(Lw, string'("----- verifying result: "));
652
        writeline(output, Lw);
653
        write(Lw, string'("  Read result:     "));
654
        hwrite(Lw, result(base_width-1 downto 0));
655
        writeline(output, Lw);
656
        write(Lw, string'("  Computed result: "));
657
        hwrite(Lw, data_read(base_width-1 downto 0));
658
        writeline(output, Lw);
659
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
660
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
661
        else
662
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
663
          assert false report "result is incorrect!!!" severity failure;
664
        end if;
665
        writeline(output, Lw);
666
 
667
      when others =>
668
        assert false report "undefined state!" severity failure;
669
    end case;
670
 
671
    if (param_count = 12) then
672
      param_count := 0;
673
    else
674
      param_count := param_count+1;
675
    end if;
676
  end loop;
677
 
678
  wait for 1 us;
679
  assert false report "End of simulation" severity failure;
680
 
681
end process;
682
 
683
------------------------------------------
684
-- Multiplier core instance
685
------------------------------------------
686 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
687 43 JonasDC
generic map(
688
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
689
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
690
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
691 70 JonasDC
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
692 94 JonasDC
  C_FIFO_AW         => C_FIFO_AW,
693 70 JonasDC
  C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
694 84 JonasDC
  C_FPGA_MAN        => C_FPGA_MAN   -- xilinx, altera are valid options
695 43 JonasDC
)
696 2 JonasDC
port map(
697 94 JonasDC
  bus_clk   => clk,
698
  core_clk  => core_clk,
699
  reset     => reset,
700 2 JonasDC
-- operand memory interface (plb shared memory)
701
  write_enable => core_write_enable,
702
  data_in      => core_data_in,
703
  rw_address   => core_rw_address,
704
  data_out     => core_data_out,
705
  collision    => core_mem_collision,
706
-- op_sel fifo interface
707
  fifo_din    => core_fifo_din,
708
  fifo_push   => core_fifo_push,
709
  fifo_full   => core_fifo_full,
710
  fifo_nopush => core_fifo_nopush,
711
-- ctrl signals
712
  start          => core_start,
713 46 JonasDC
  exp_m          => core_exp_m,
714 2 JonasDC
  ready          => core_ready,
715
  x_sel_single   => core_x_sel_single,
716
  y_sel_single   => core_y_sel_single,
717
  dest_op_single => core_dest_op_single,
718
  p_sel          => core_p_sel,
719 70 JonasDC
  calc_time      => calc_time,
720 84 JonasDC
  modulus_sel    => '0'
721 2 JonasDC
);
722
 
723
end test;

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