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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [msec_axi_tb.vhd] - Blame information for rev 94

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1 90 JonasDC
----------------------------------------------------------------------  
2
----  msec_axi_tb                                                 ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the AXI-Lite interface of the modular       ----
10
----    simultaneous exponentiation core. Performs some           ----
11
----    exponentiations to verify the design                      ----
12
----    Takes input parameters from in/sim_input.txt en writes    ----
13
----    result and output to out/axi_sim_output.txt. The AXI bus  ----
14
----    transfers ar written to out/axi_bus_output                ----
15
----                                                              ----
16
----  Dependencies:                                               ----
17
----    - msec_ipcore_axilite                                     ----
18
----                                                              ----
19
----  Authors:                                                    ----
20
----      - Geoffrey Ottoy, DraMCo research group                 ----
21
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
22
----                                                              ---- 
23
---------------------------------------------------------------------- 
24
----                                                              ---- 
25
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
26
----                                                              ---- 
27
---- This source file may be used and distributed without         ---- 
28
---- restriction provided that this copyright statement is not    ---- 
29
---- removed from the file and that any derivative work contains  ---- 
30
---- the original copyright notice and the associated disclaimer. ---- 
31
----                                                              ---- 
32
---- This source file is free software; you can redistribute it   ---- 
33
---- and/or modify it under the terms of the GNU Lesser General   ---- 
34
---- Public License as published by the Free Software Foundation; ---- 
35
---- either version 2.1 of the License, or (at your option) any   ---- 
36
---- later version.                                               ---- 
37
----                                                              ---- 
38
---- This source is distributed in the hope that it will be       ---- 
39
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
40
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
41
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
42
---- details.                                                     ---- 
43
----                                                              ---- 
44
---- You should have received a copy of the GNU Lesser General    ---- 
45
---- Public License along with this source; if not, download it   ---- 
46
---- from http://www.opencores.org/lgpl.shtml                     ---- 
47
----                                                              ---- 
48
----------------------------------------------------------------------
49
 
50
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.std_logic_unsigned.all;
53
use ieee.std_logic_arith.all;
54
 
55
library std;
56
use std.textio.all;
57
 
58
library ieee;
59
use ieee.std_logic_textio.all;
60
 
61
entity msec_axi_tb is
62
end msec_axi_tb;
63
 
64
architecture arch of msec_axi_tb is
65
  -- constants
66
  constant CLK_PERIOD : time := 10 ns;
67
  constant CORE_CLK_PERIOD : time := 4 ns;
68
  constant C_S_AXI_DATA_WIDTH : integer := 32;
69
  constant C_S_AXI_ADDR_WIDTH : integer := 32;
70
 
71
  file output : text open write_mode is "out/axi_sim_output.txt";
72
  file axi_dbg : text open write_mode is "out/axi_bus_output.txt";
73
  file input  : text open read_mode is "src/sim_input.txt";
74
 
75
  ------------------------------------------------------------------
76
  -- Core parameters
77
  ------------------------------------------------------------------
78
  constant C_NR_BITS_TOTAL   : integer := 1536;
79
  constant C_NR_STAGES_TOTAL : integer := 96;
80
  constant C_NR_STAGES_LOW   : integer := 32;
81
  constant C_SPLIT_PIPELINE  : boolean := true;
82 94 JonasDC
  constant C_FIFO_AW         : integer := 7; -- set to log2( (maximum exponent width)/16 )
83
  constant C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
84 90 JonasDC
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
85
  constant C_BASEADDR        : std_logic_vector(0 to 31) := x"A0000000";
86
  constant C_HIGHADDR        : std_logic_vector(0 to 31) := x"A0007FFF";
87
 
88
  -- extra calculated constants
89
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
90
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
91
 
92
  signal core_clk     : std_logic := '0';
93
  -------------------------
94
  -- AXI4lite interface
95
  -------------------------
96
  --- Global signals
97
  signal S_AXI_ACLK    : std_logic;
98
  signal S_AXI_ARESETN : std_logic;
99
  --- Write address channel
100
  signal S_AXI_AWADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
101
  signal S_AXI_AWVALID : std_logic;
102
  signal S_AXI_AWREADY : std_logic;
103
  --- Write data channel
104
  signal S_AXI_WDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
105
  signal S_AXI_WVALID : std_logic;
106
  signal S_AXI_WREADY : std_logic;
107
  signal S_AXI_WSTRB  : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
108
  --- Write response channel
109
  signal S_AXI_BVALID : std_logic;
110
  signal S_AXI_BREADY : std_logic;
111
  signal S_AXI_BRESP  : std_logic_vector(1 downto 0);
112
  --- Read address channel
113
  signal S_AXI_ARADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
114
  signal S_AXI_ARVALID : std_logic;
115
  signal S_AXI_ARREADY : std_logic;
116
  --- Read data channel
117
  signal S_AXI_RDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
118
  signal S_AXI_RVALID : std_logic;
119
  signal S_AXI_RREADY : std_logic;
120
  signal S_AXI_RRESP  : std_logic_vector(1 downto 0);
121
 
122
  -- CORE control reg bits
123
  signal core_control_reg    : std_logic_vector(31 downto 0) := (others=>'0');
124
  signal core_start          : std_logic;
125
  signal core_exp_m          : std_logic;
126
  signal core_p_sel          : std_logic_vector(1 downto 0);
127
  signal core_dest_op_single : std_logic_vector(1 downto 0);
128
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
129
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
130
  signal core_modulus_sel    : std_logic;
131
  signal calc_time           : std_logic;
132
  signal IntrEvent           : std_logic;
133
 
134
begin
135
 
136
  -- map the core control bits to the core control register
137
  core_control_reg(31 downto 30) <= core_p_sel;
138
  core_control_reg(29 downto 28) <= core_dest_op_single;
139
  core_control_reg(27 downto 26) <= core_x_sel_single;
140
  core_control_reg(25 downto 24) <= core_y_sel_single;
141
  core_control_reg(23) <= core_start;
142
  core_control_reg(22) <= core_exp_m;
143
  core_control_reg(21) <= core_modulus_sel;
144
 
145
  ------------------------------------------
146
  -- Generate S_AXI_ACLK
147
  ------------------------------------------
148
  clk_process : process
149
  begin
150
    while (true) loop
151
      S_AXI_ACLK <= '0';
152
      wait for CLK_PERIOD/2;
153
      S_AXI_ACLK <= '1';
154
      wait for CLK_PERIOD/2;
155
    end loop;
156
  end process;
157
 
158
  core_clk_process : process
159
  begin
160
    while (true) loop
161
      core_clk <= '0';
162
      wait for CORE_CLK_PERIOD/2;
163
      core_clk <= '1';
164
      wait for CORE_CLK_PERIOD/2;
165
    end loop;
166
  end process;
167
 
168
 
169
  stim_proc : process
170
    -- variables to read file
171
    variable L : line;
172
    variable Lw : line;
173
    variable La : line;
174
 
175
    -- constants for memory space selection
176
    constant op_modulus : std_logic_vector(2 downto 0) := "000";
177
    constant op_0 : std_logic_vector(2 downto 0) := "001";
178
    constant op_1 : std_logic_vector(2 downto 0) := "010";
179
    constant op_2 : std_logic_vector(2 downto 0) := "011";
180
    constant op_3 : std_logic_vector(2 downto 0) := "100";
181
    constant fifo : std_logic_vector(2 downto 0) := "101";
182
    constant control_reg : std_logic_vector(2 downto 0) := "110";
183
 
184
    procedure waitclk(n : natural := 1) is
185
    begin
186
      for i in 1 to n loop
187
        wait until rising_edge(S_AXI_ACLK);
188
      end loop;
189
    end waitclk;
190
 
191
    procedure axi_write( variable address : std_logic_vector(31 downto 0);
192
                         variable data    : std_logic_vector(31 downto 0) ) is
193
      variable counter : integer := 0;
194
    begin
195
      -- place address on the bus
196
      wait until rising_edge(S_AXI_ACLK);
197
      S_AXI_AWADDR <= address;
198
      S_AXI_AWVALID <= '1';
199
      S_AXI_WDATA <= data;
200
      S_AXI_WVALID <= '1';
201
      S_AXI_WSTRB <= "1111";
202
      while (counter /= 2) loop -- wait for slave response
203
        wait until rising_edge(S_AXI_ACLK);
204
        if (S_AXI_AWREADY='1') then
205
          S_AXI_AWVALID <= '0';
206
          counter := counter+1;
207
        end if;
208
        if (S_AXI_WREADY='1') then
209
          S_AXI_WVALID <= '0';
210
          counter := counter+1;
211
        end if;
212
      end loop;
213
      S_AXI_BREADY <= '1';
214
      if S_AXI_BVALID/='1' then
215
        wait until S_AXI_BVALID='1';
216
      end if;
217
 
218
      write(La, string'("Wrote "));
219
      hwrite(La, data);
220
      write(La, string'(" to   "));
221
      hwrite(La, address);
222
 
223
      if (S_AXI_BRESP /= "00") then
224
        write(La, string'("   --> Error! Status: "));
225
        write(La, S_AXI_BRESP);
226
      end if;
227
      writeline(axi_dbg, La);
228
 
229
      wait until rising_edge(S_AXI_ACLK);
230
      S_AXI_BREADY <= '0';
231
    end axi_write;
232
 
233
    procedure axi_read( variable address  : std_logic_vector(31 downto 0);
234
                        variable data : out std_logic_vector(31 downto 0) ) is
235
    begin
236
      -- place address on the bus
237
      wait until rising_edge(S_AXI_ACLK);
238
      S_AXI_ARADDR <= address;
239
      S_AXI_ARVALID <= '1';
240
      wait until S_AXI_ARREADY='1';
241
      wait until rising_edge(S_AXI_ACLK);
242
      S_AXI_ARVALID <= '0';
243
      -- wait for read data
244
      S_AXI_RREADY <= '1';
245
      wait until S_AXI_RVALID='1';
246
      wait until rising_edge(S_AXI_ACLK);
247
 
248
      data := S_AXI_RDATA;
249
      write(La, string'("Read  "));
250
      hwrite(La, S_AXI_RDATA);
251
      write(La, string'(" from "));
252
      hwrite(La, address);
253
 
254
      if (S_AXI_RRESP /= "00") then
255
        write(La, string'("   --> Error! Status: "));
256
        write(La, S_AXI_RRESP);
257
      end if;
258
      writeline(axi_dbg, La);
259
      S_AXI_RREADY <= '0';
260
 
261
      --assert false report "Wrote " & " to " & " Status=" & to_string(S_AXI_BRESP) severity note;
262
    end axi_read;
263
 
264
    procedure axi_write_control_reg is
265
      variable address : std_logic_vector(31 downto 0);
266
      variable data    : std_logic_vector(31 downto 0);
267
    begin
268
      wait until rising_edge(S_AXI_ACLK);
269
      address := C_BASEADDR+x"00006000";
270
      data := core_control_reg;
271
      axi_write(address, data);
272
    end axi_write_control_reg;
273
 
274
    procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
275
                    variable op_data : std_logic_vector(2047 downto 0)) is
276
      variable address : std_logic_vector(31 downto 0);
277
      variable zero    : std_logic_vector(31 downto 0) := (others=>'0');
278
    begin
279
      -- set the start address
280
      address := C_BASEADDR(0 to 15) & '0' & op_sel & "0000" & "000000" & "00";
281
      -- write operand per 32 bits
282
      for i in 0 to (C_NR_BITS_TOTAL/32)-1 loop
283
        case (core_p_sel) is
284
          when "11" =>
285
            axi_write(address, op_data(((i+1)*32)-1 downto (i*32)));
286
          when "01" =>
287
            if (i < 16) then axi_write(address, op_data(((i+1)*32)-1 downto (i*32)));
288
            else axi_write(address, zero); end if;
289
          when "10" =>
290
            if (i >= 16) then axi_write(address, op_data(((i-15)*32)-1 downto ((i-16)*32)));
291
            else axi_write(address, zero); end if;
292
          when others =>
293
            axi_write(address, zero);
294
        end case;
295
        -- next address is 32 further
296
        address := address + "100";
297
      end loop;
298
    end loadOp;
299
 
300
    procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
301
                    variable op_data  : out std_logic_vector(2047 downto 0);
302
                    variable op_width : integer) is
303
      variable address : std_logic_vector(31 downto 0);
304
      variable data    : std_logic_vector(31 downto 0);
305
    begin
306
      -- set destination operand, cause only can readfrom destination operand
307
      case op_sel is
308
        when "001" => core_dest_op_single <= "00";
309
        when "010" => core_dest_op_single <= "01";
310
        when "011" => core_dest_op_single <= "10";
311
        when "100" => core_dest_op_single <= "11";
312
        when others => core_dest_op_single <= "00";
313
      end case;
314
      axi_write_control_reg;
315
 
316
      -- set the start address
317
      if (core_p_sel = "10") then
318
        address := C_BASEADDR(0 to 15) & '0' & op_sel & "0000" & "010000" & "00";
319
      else
320
        address := C_BASEADDR(0 to 15) & '0' & op_sel & "0000" & "000000" & "00";
321
      end if;
322
      -- read the data
323
      for i in 0 to (op_width/32)-1 loop
324
        axi_read(address, data);
325
        op_data(((i+1)*32)-1 downto (i*32)) := data;
326
        -- next address is 32 further
327
        address := address + "100";
328
      end loop;
329
    end readOp;
330
 
331
    procedure loadFifo(variable data : std_logic_vector(31 downto 0)) is
332
      variable address : std_logic_vector(31 downto 0);
333
    begin
334
      -- set the start address
335
      address := C_BASEADDR(0 to 15) & '0' & fifo & "0000" & "000000" & "00";
336
      axi_write(address, data);
337
    end loadFifo;
338
 
339
    function ToString(constant Timeval : time) return string is
340
      variable StrPtr : line;
341
    begin
342
      write(StrPtr,Timeval);
343
      return StrPtr.all;
344
    end ToString;
345
 
346
 
347
    variable base_width : integer;
348
    variable exponent_width : integer;
349
    variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
350
    variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
351
    variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
352
    variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
353
    variable m : std_logic_vector(2047 downto 0) := (others=>'0');
354
    variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
355
    variable R : std_logic_vector(2047 downto 0) := (others=>'0');
356
    variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
357
    variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
358
    variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
359
    variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
360
    variable result : std_logic_vector(2047 downto 0) := (others=>'0');
361
    variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
362
    variable good_value : boolean;
363
    variable param_count : integer := 0;
364
    variable temp_data : std_logic_vector(31 downto 0);
365
 
366
    variable timer : time;
367
  begin
368
 
369
    write(Lw, string'("----------------------------------------------"));
370
    writeline(output, Lw);
371
    write(Lw, string'("--            AXI BUS SIMULATION            --"));
372
    writeline(output, Lw);
373
    write(Lw, string'("----------------------------------------------"));
374
    writeline(output, Lw);
375
    -- axi bus initialisation
376
    S_AXI_AWADDR <= (others=>'0');
377
    S_AXI_AWVALID <= '0';
378
    S_AXI_WDATA <= (others=>'0');
379
    S_AXI_WVALID <= '0';
380
    S_AXI_WSTRB <= (others=>'0');
381
    S_AXI_BREADY <= '0';
382
    S_AXI_ARADDR <= (others=>'0');
383
    S_AXI_ARVALID <= '0';
384
    S_AXI_RREADY <= '0';
385
    -- control signals initialisation
386
    core_start <= '0';
387
    core_exp_m <= '0';
388
    core_x_sel_single <= "00";
389
    core_y_sel_single <= "01";
390
    core_dest_op_single <= "01";
391
    core_p_sel <= "11";
392
    core_modulus_sel <= '0';
393
    -- reset
394
    S_AXI_ARESETN <= '0';
395
    waitclk(10);
396
    S_AXI_ARESETN <= '1';
397
    waitclk(20);
398
 
399
 
400
    while not endfile(input) loop
401
      readline(input, L); -- read next line
402
      next when L(1)='-'; -- skip comment lines
403
      -- read input values
404
      case param_count is
405
        when 0 => -- base width
406
          read(L, base_width, good_value);
407
          assert good_value report "Can not read base width" severity failure;
408
          assert false report "Simulating exponentiation" severity note;
409
          write(Lw, string'("----------------------------------------------"));
410
          writeline(output, Lw);
411
          write(Lw, string'("--              EXPONENTIATION              --"));
412
          writeline(output, Lw);
413
          write(Lw, string'("----------------------------------------------"));
414
          writeline(output, Lw);
415
          write(Lw, string'("----- Variables used:"));
416
          writeline(output, Lw);
417
          write(Lw, string'("base width: "));
418
          write(Lw, base_width);
419
          writeline(output, Lw);
420
          case (base_width) is
421
            when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
422
            when others =>
423
              write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
424
              assert false report "incompatible base width!!!" severity failure;
425
          end case;
426
 
427
        when 1 => -- exponent width
428
          read(L, exponent_width, good_value);
429
          assert good_value report "Can not read exponent width" severity failure;
430
          write(Lw, string'("exponent width: "));
431
          write(Lw, exponent_width);
432
          writeline(output, Lw);
433
 
434
        when 2 => -- g0
435
          hread(L, g0(base_width-1 downto 0), good_value);
436
          assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
437
          write(Lw, string'("g0: "));
438
          hwrite(Lw, g0(base_width-1 downto 0));
439
          writeline(output, Lw);
440
 
441
        when 3 => -- g1
442
          hread(L, g1(base_width-1 downto 0), good_value);
443
          assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
444
          write(Lw, string'("g1: "));
445
          hwrite(Lw, g1(base_width-1 downto 0));
446
          writeline(output, Lw);
447
 
448
        when 4 => -- e0
449
          hread(L, e0(exponent_width-1 downto 0), good_value);
450
          assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
451
          write(Lw, string'("e0: "));
452
          hwrite(Lw, e0(exponent_width-1 downto 0));
453
          writeline(output, Lw);
454
 
455
        when 5 => -- e1
456
          hread(L, e1(exponent_width-1 downto 0), good_value);
457
          assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
458
          write(Lw, string'("e1: "));
459
          hwrite(Lw, e1(exponent_width-1 downto 0));
460
          writeline(output, Lw);
461
 
462
        when 6 => -- m
463
          hread(L, m(base_width-1 downto 0), good_value);
464
          assert good_value report "Can not read m! (wrong lenght?)" severity failure;
465
          write(Lw, string'("m:  "));
466
          hwrite(Lw, m(base_width-1 downto 0));
467
          writeline(output, Lw);
468
 
469
        when 7 => -- R^2
470
          hread(L, R2(base_width-1 downto 0), good_value);
471
          assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
472
          write(Lw, string'("R2: "));
473
          hwrite(Lw, R2(base_width-1 downto 0));
474
          writeline(output, Lw);
475
 
476
        when 8 => -- R
477
          hread(L, R(base_width-1 downto 0), good_value);
478
          assert good_value report "Can not read R! (wrong lenght?)" severity failure;
479
 
480
        when 9 => -- gt0
481
          hread(L, gt0(base_width-1 downto 0), good_value);
482
          assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
483
 
484
        when 10 => -- gt1
485
          hread(L, gt1(base_width-1 downto 0), good_value);
486
          assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
487
 
488
        when 11 => -- gt01
489
          hread(L, gt01(base_width-1 downto 0), good_value);
490
          assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
491
 
492
          -- select pipeline for all computations
493
          ----------------------------------------
494
          writeline(output, Lw);
495
          write(Lw, string'("----- Selecting pipeline: "));
496
          writeline(output, Lw);
497
          case (base_width) is
498
            when C_NR_BITS_TOTAL =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
499
            when NR_BITS_HIGH =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
500
            when NR_BITS_LOW  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
501
            when others =>
502
              write(Lw, string'("  Invallid bitwidth for design"));
503
              assert false report "impossible basewidth!" severity failure;
504
          end case;
505
          axi_write_control_reg;
506
          writeline(output, Lw);
507
 
508
          writeline(output, Lw);
509
          write(Lw, string'("----- Writing operands:"));
510
          writeline(output, Lw);
511
 
512
          -- load the modulus
513
          --------------------
514
          loadOp(op_modulus, m); -- visual check needed
515
          write(Lw, string'("  m written"));
516
          writeline(output, Lw);
517
 
518
          -- load g0
519
          -----------
520
          loadOp(op_0, g0);
521
          -- verify
522
          readOp(op_0, data_read, base_width);
523
          if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
524
            write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
525
          else
526
            write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
527
            assert false report "Load g0 to op0 data verify failed!!" severity failure;
528
          end if;
529
 
530
          -- load g1
531
          -----------
532
          loadOp(op_1, g1);
533
          -- verify
534
          readOp(op_1, data_read, base_width);
535
          if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
536
            write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
537
          else
538
            write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
539
            assert false report "Load g1 to op1 data verify failed!!" severity failure;
540
          end if;
541
 
542
          -- load R2
543
          -----------
544
          loadOp(op_2, R2);
545
          -- verify
546
          readOp(op_2, data_read, base_width);
547
          if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
548
            write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
549
          else
550
            write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
551
            assert false report "Load R2 to op2 data verify failed!!" severity failure;
552
          end if;
553
 
554
          -- load a=1
555
          ------------
556
          loadOp(op_3, one);
557
          -- verify
558
          readOp(op_3, data_read, base_width);
559
          if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
560
            write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
561
          else
562
            write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
563
            assert false report "Load 1 to op3 data verify failed!!" severity failure;
564
          end if;
565
 
566
          writeline(output, Lw);
567
          write(Lw, string'("----- Pre-computations: "));
568
          writeline(output, Lw);
569
 
570
          -- compute gt0
571
          ---------------
572
          core_x_sel_single <= "00"; -- g0
573
          core_y_sel_single <= "10"; -- R^2
574
          core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
575
          axi_write_control_reg;
576
          timer := NOW;
577
          core_start <= '1';
578
          axi_write_control_reg;
579
          core_start <= '0';
580
          axi_write_control_reg;
581
          wait until IntrEvent = '1';
582
          timer := NOW-timer;
583
          waitclk(10);
584
          readOp(op_0, data_read, base_width);
585
          write(Lw, string'("  Computed gt0: "));
586
          hwrite(Lw, data_read(base_width-1 downto 0));
587
          writeline(output, Lw);
588
          write(Lw, string'("  Read gt0:     "));
589
          hwrite(Lw, gt0(base_width-1 downto 0));
590
          writeline(output, Lw);
591
          write(Lw, string'("  => calc time is "));
592
          write(Lw, string'(ToString(timer)));
593
          writeline(output, Lw);
594
          write(Lw, string'("  => expected time is "));
595
          write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
596
          writeline(output, Lw);
597
          if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
598
            write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
599
          else
600
            write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
601
            assert false report "gt0 is incorrect!!!" severity failure;
602
          end if;
603
 
604
          -- compute gt1
605
          ---------------
606
          core_x_sel_single <= "01"; -- g1
607
          core_y_sel_single <= "10"; -- R^2
608
          core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
609
          timer := NOW;
610
          core_start <= '1';
611
          axi_write_control_reg;
612
          core_start <= '0';
613
          axi_write_control_reg;
614
          wait until IntrEvent = '1';
615
          timer := NOW-timer;
616
          waitclk(10);
617
          readOp(op_1, data_read, base_width);
618
          write(Lw, string'("  Computed gt1: "));
619
          hwrite(Lw, data_read(base_width-1 downto 0));
620
          writeline(output, Lw);
621
          write(Lw, string'("  Read gt1:     "));
622
          hwrite(Lw, gt1(base_width-1 downto 0));
623
          writeline(output, Lw);
624
          write(Lw, string'("  => calc time is "));
625
          write(Lw, string'(ToString(timer)));
626
          writeline(output, Lw);
627
          write(Lw, string'("  => expected time is "));
628
          write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
629
          writeline(output, Lw);
630
          if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
631
            write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
632
          else
633
            write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
634
            assert false report "gt1 is incorrect!!!" severity failure;
635
          end if;
636
 
637
          -- compute a
638
          -------------
639
          core_x_sel_single <= "10"; -- R^2
640
          core_y_sel_single <= "11"; -- 1
641
          core_dest_op_single <= "11"; -- op_3 = (R) mod m
642
          core_start <= '1';
643
          axi_write_control_reg;
644
          timer := NOW;
645
          core_start <= '0';
646
          axi_write_control_reg;
647
          wait until IntrEvent = '1';
648
          timer := NOW-timer;
649
          waitclk(10);
650
          readOp(op_3, data_read, base_width);
651
          write(Lw, string'("  Computed a=(R)mod m: "));
652
          hwrite(Lw, data_read(base_width-1 downto 0));
653
          writeline(output, Lw);
654
          write(Lw, string'("  Read (R)mod m:       "));
655
          hwrite(Lw, R(base_width-1 downto 0));
656
          writeline(output, Lw);
657
          write(Lw, string'("  => calc time is "));
658
          write(Lw, string'(ToString(timer)));
659
          writeline(output, Lw);
660
          write(Lw, string'("  => expected time is "));
661
          write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
662
          writeline(output, Lw);
663
          if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
664
            write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
665
          else
666
            write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
667
            assert false report "(R)mod m is incorrect!!!" severity failure;
668
          end if;
669
 
670
          -- compute gt01
671
          ---------------
672
          core_x_sel_single <= "00"; -- gt0
673
          core_y_sel_single <= "01"; -- gt1
674
          core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
675
          core_start <= '1';
676
          axi_write_control_reg;
677
          timer := NOW;
678
          core_start <= '0';
679
          axi_write_control_reg;
680
          wait until IntrEvent = '1';
681
          timer := NOW-timer;
682
          waitclk(10);
683
          readOp(op_2, data_read, base_width);
684
          write(Lw, string'("  Computed gt01: "));
685
          hwrite(Lw, data_read(base_width-1 downto 0));
686
          writeline(output, Lw);
687
          write(Lw, string'("  Read gt01:     "));
688
          hwrite(Lw, gt01(base_width-1 downto 0));
689
          writeline(output, Lw);
690
          write(Lw, string'("  => calc time is "));
691
          write(Lw, string'(ToString(timer)));
692
          writeline(output, Lw);
693
          write(Lw, string'("  => expected time is "));
694
          write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
695
          writeline(output, Lw);
696
          if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
697
            write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
698
          else
699
            write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
700
            assert false report "gt01 is incorrect!!!" severity failure;
701
          end if;
702
 
703
          -- load exponent fifo
704
          ----------------------
705
          writeline(output, Lw);
706
          write(Lw, string'("----- Loading exponent fifo: "));
707
          writeline(output, Lw);
708
          for i in (exponent_width/16)-1 downto 0 loop
709
            temp_data := e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
710
            LoadFifo(temp_data);
711
          end loop;
712
          waitclk(10);
713
          write(Lw, string'("  => Done"));
714
          writeline(output, Lw);
715
 
716
          -- start exponentiation
717
          ------------------------
718
          writeline(output, Lw);
719
          write(Lw, string'("----- Starting exponentiation: "));
720
          writeline(output, Lw);
721
          core_exp_m <= '1';
722
          timer := NOW;
723
          core_start <= '1';
724
          axi_write_control_reg;
725
          core_start <= '0';
726
          axi_write_control_reg;
727
          wait until IntrEvent='1';
728
          timer := NOW-timer;
729
          waitclk(10);
730
          write(Lw, string'("  => calc time is "));
731
          write(Lw, string'(ToString(timer)));
732
          writeline(output, Lw);
733
          write(Lw, string'("  => expected time is "));
734
          write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
735
          writeline(output, Lw);
736
          write(Lw, string'("  => Done"));
737
          core_exp_m <= '0';
738
          writeline(output, Lw);
739
 
740
          -- post-computations
741
          ---------------------
742
          writeline(output, Lw);
743
          write(Lw, string'("----- Post-computations: "));
744
          writeline(output, Lw);
745
          -- load in 1 to operand 2
746
          loadOp(op_2, one);
747
          -- verify
748
          readOp(op_2, data_read, base_width);
749
          if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
750
            write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
751
          else
752
            write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
753
            assert false report "Load 1 to op2 data verify failed!!" severity failure;
754
          end if;
755
          -- compute result
756
          core_x_sel_single <= "11"; -- a
757
          core_y_sel_single <= "10"; -- 1
758
          core_dest_op_single <= "11"; -- op_3 = (a) mod m
759
          timer := NOW;
760
          core_start <= '1';
761
          axi_write_control_reg;
762
          core_start <= '0';
763
          axi_write_control_reg;
764
          wait until IntrEvent = '1';
765
          timer := NOW-timer;
766
          waitclk(10);
767
          readOp(op_3, data_read, base_width);
768
          write(Lw, string'("  Computed result: "));
769
          hwrite(Lw, data_read(base_width-1 downto 0));
770
          writeline(output, Lw);
771
          write(Lw, string'("  => calc time is "));
772
          write(Lw, string'(ToString(timer)));
773
          writeline(output, Lw);
774
          write(Lw, string'("  => expected time is "));
775
          write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
776
          writeline(output, Lw);
777
 
778
        when 12 => -- check with result
779
          hread(L, result(base_width-1 downto 0), good_value);
780
          assert good_value report "Can not read result! (wrong lenght?)" severity failure;
781
          writeline(output, Lw);
782
          write(Lw, string'("----- verifying result: "));
783
          writeline(output, Lw);
784
          write(Lw, string'("  Read result:     "));
785
          hwrite(Lw, result(base_width-1 downto 0));
786
          writeline(output, Lw);
787
          write(Lw, string'("  Computed result: "));
788
          hwrite(Lw, data_read(base_width-1 downto 0));
789
          writeline(output, Lw);
790
          if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
791
            write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
792
          else
793
            write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
794
            assert false report "result is incorrect!!!" severity failure;
795
          end if;
796
          writeline(output, Lw);
797
 
798
        when others =>
799
          assert false report "undefined state!" severity failure;
800
      end case;
801
 
802
      if (param_count = 12) then
803
        param_count := 0;
804
      else
805
        param_count := param_count+1;
806
      end if;
807
    end loop;
808
 
809
    wait for 1 us;
810
    assert false report "End of simulation" severity failure;
811
 
812
  end process;
813
 
814
 
815
  -------------------------
816
  -- Unit Under Test
817
  -------------------------
818
  uut : entity work.msec_ipcore_axilite
819
  generic map(
820
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
821
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
822
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
823
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
824 94 JonasDC
    C_FIFO_AW         => C_FIFO_AW,
825 90 JonasDC
    C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
826
    C_FPGA_MAN        => C_FPGA_MAN,   -- xilinx, altera are valid options
827
    C_BASEADDR        => C_BASEADDR,
828
    C_HIGHADDR        => C_HIGHADDR
829
  )
830
  port map(
831
    --USER ports
832
    calc_time => calc_time,
833
    IntrEvent => IntrEvent,
834 94 JonasDC
    core_clk  => core_clk,
835 90 JonasDC
    -------------------------
836
    -- AXI4lite interface
837
    -------------------------
838
    --- Global signals
839
    S_AXI_ACLK    => S_AXI_ACLK,
840
    S_AXI_ARESETN => S_AXI_ARESETN,
841
    --- Write address channel
842
    S_AXI_AWADDR  => S_AXI_AWADDR,
843
    S_AXI_AWVALID => S_AXI_AWVALID,
844
    S_AXI_AWREADY => S_AXI_AWREADY,
845
    --- Write data channel
846
    S_AXI_WDATA  => S_AXI_WDATA,
847
    S_AXI_WVALID => S_AXI_WVALID,
848
    S_AXI_WREADY => S_AXI_WREADY,
849
    S_AXI_WSTRB  => S_AXI_WSTRB,
850
    --- Write response channel
851
    S_AXI_BVALID => S_AXI_BVALID,
852
    S_AXI_BREADY => S_AXI_BREADY,
853
    S_AXI_BRESP  => S_AXI_BRESP,
854
    --- Read address channel
855
    S_AXI_ARADDR  => S_AXI_ARADDR,
856
    S_AXI_ARVALID => S_AXI_ARVALID,
857
    S_AXI_ARREADY => S_AXI_ARREADY,
858
    --- Read data channel
859
    S_AXI_RDATA  => S_AXI_RDATA,
860
    S_AXI_RVALID => S_AXI_RVALID,
861
    S_AXI_RREADY => S_AXI_RREADY,
862
    S_AXI_RRESP  => S_AXI_RRESP
863
  );
864
 
865
end arch;
866
 

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