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1 47 JonasDC
\chapter{PLB interface}
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\section{Structure}
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The Processor Local Bus interface for this core is structured as in Figure~\ref{PLBstructure}. The core acts as a slave
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to the PLB bus. The PLB v4.6 Slave\cite{XilinxPLB} logic translates the interface to a lower level IP Interconnect
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Interface (IPIC).
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This is then used to connect the core internal components to. The user logic contains the exponentiation core and the
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control register for the core its control inputs and outputs. An internal interrupt controller\cite{XilinxIntr} handles
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the outgoing interrupt requests and a software reset module is provided to be able to reset the IP core at runtime. This
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bus interface is created using the Create or Import Peripheral'' wizard from Xilinx Platform Studio.\\
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\begin{figure}[H]
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\centering
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=7cm]{pictures/plb_interface.pdf}
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\caption{PLB IP core structure}
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\label{PLBstructure}
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\end{figure}
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\newpage
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\section{Parameters}
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This section describes the parameters used to configure the core, only the relevant parameters are discussed. PLB
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specific parameters are left to the user to configure. The IP core specific parameters and their respective use are
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listed in the table below.
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\begin{center}
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        \begin{tabular}{|l|p{6.5cm}|c|l|}
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                \hline
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                \rowcolor{Gray}
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                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
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                \hline
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                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
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                \hline
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                \verb|C_FIFO_DEPTH| & depth of the generic FIFO, only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"|  & integer & 32 \bigstrut\\
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                \hline
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                \verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
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                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
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                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
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                                                & \verb|"asym"| : use asymmetric RAMs & & \\
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                                                & (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
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                \hline
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                \verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
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                                                & \verb|"xilinx"| or \verb|"altera"| &  &  \bigstrut\\
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                \hline
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                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_M_BASEADDR| & base address for the modulus memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_M_HIGHADDR| & high address for the modulus memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_OP0_BASEADDR| & base address for the operand 0 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_OP0_HIGHADDR| & high address for the operand 0 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_OP1_BASEADDR| & base address for the operand 1 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_OP1_HIGHADDR| & high address for the operand 1 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_OP2_BASEADDR| & base address for the operand 2 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_OP2_HIGHADDR| & high address for the operand 2 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_OP3_BASEADDR| & base address for the operand 3 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_OP3_HIGHADDR| & high address for the operand 3 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \verb|C_FIFO_BASEADDR| & base address for the FIFO memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_FIFO_HIGHADDR| & high address for the FIFO memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \multicolumn{4}{|l|}{\textit{\textbf{Multiplier configuration}}} \\
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                \hline
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                \verb|C_NR_BITS_TOTAL| & total width of the multiplier in bits & integer & 1536\bigstrut\\
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                \hline
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                \verb|C_NR_STAGES_TOTAL| & total number of stages in the pipeline & integer & 96\bigstrut\\
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                \hline
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                \verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
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                \hline
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                \verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
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                \hline
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        \end{tabular}%
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\end{center}
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%\newline
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The complete IP core's memory space can be controlled. As can be seen, the operand, modulus and FIFO memory space can be
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chosen separately from the IP core's memory space which hold the registers for control, software reset and interrupt
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control. The core's memory space must have a minimum width of 1K byte for all registers to be accessible. For the FIFO
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memory space, a minimum width of 4 byte is needed, since the FIFO is only 32 bit wide. The memory space width for the
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operands and the modulus need a minimum width equal to the total multiplier width.\\
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There are 4 parameters to configure the multiplier. These values define the width of the multiplier operands and the
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number of pipeline stages. If \verb|C_SPLIT_PIPELINE| is false, only operands with a width of\\\verb|C_NR_BITS_TOTAL| are
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valid. Else if \verb|C_SPLIT_PIPELINE| is true, 3 operand widths can be supported:
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\begin{itemize}
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  \item the length of the full pipeline ($C\_NR\_BITS\_TOTAL$)
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  \item the length of the lower pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot C\_NR\_STAGES\_LOW$)
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  \item the length of the higher pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot (C\_NR\_STAGES\_TOTAL - C\_NR\_STAGES\_LOW$)
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\end{itemize}
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\section{IO ports}
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\begin{tabular}{|l|c|c|l|}
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        \hline
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        \rowcolor{Gray}
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        \textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \\
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        \hline
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        \multicolumn{4}{|l|}{\textit{\textbf{PLB bus connections}}} \\
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        \hline
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        \verb|SPLB_Clk| & 1     & in & see note 1 \\
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        \hline
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        \verb|SPLB_Rst| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_ABus| & 32    & in & see note 1 \\
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        \hline
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        \verb|PLB_PAValid| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_masterID| & 3     & in & see note 1 \\
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        \hline
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        \verb|PLB_RNW| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_BE| & 4     & in & see note 1 \\
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        \hline
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        \verb|PLB_size| & 4     & in & see note 1 \\
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        \hline
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        \verb|PLB_type| & 3     & in & see note 1 \\
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        \hline
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        \verb|PLB_wrDBus| & 32    & in & see note 1 \\
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        \hline
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        \verb|Sl_addrAck| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_SSize| & 2     & out & see note 1 \\
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        \hline
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        \verb|Sl_wait| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_rearbitrate| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_wrDack| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_wrComp| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_rdBus| & 32    & out & see note 1 \\
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        \hline
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        \verb|Sl_MBusy| & 8     & out & see note 1 \\
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        \hline
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        \verb|Sl_MWrErr| & 8     & out & see note 1 \\
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        \hline
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        \verb|Sl_MRdErr| & 8     & out & see note 1 \\
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        \hline
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        \multicolumn{4}{|l|}{\textit{\textbf{unused PLB signals}}} \\
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        \hline
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        \verb|PLB_UABus| & 32    & in & see note 1 \\
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        \hline
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        \verb|PLB_SAValid| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_rdPrim| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_wrPrim| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_abort| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_busLock| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_MSize| & 2     & in & see note 1 \\
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        \hline
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        \verb|PLB_TAttribute| & 16    & in & see note 1 \\
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        \hline
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        \verb|PLB_lockerr| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_wrBurst| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_rdBurst| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_wrPendReq| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_rdPendReq| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_rdPendPri| & 2     & in & see note 1 \\
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        \hline
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        \verb|PLB_wrPendPri| & 2     & in & see note 1 \\
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        \hline
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        \verb|PLB_reqPri| & 2     & in & see note 1 \\
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        \hline
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        \verb|Sl_wrBTerm| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_rdWdAddr| & 4     & out & see note 1 \\
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        \hline
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        \verb|Sl_rdBTerm| & 1     & out & see note 1 \\
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        \hline
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        \verb|Sl_MIRQ| & 8     & out & see note 1 \\
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        \hline
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        \multicolumn{4}{|l|}{\textit{\textbf{Core signals}}} \\
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        \hline
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        \verb|IP2INTC_Irpt| & 1     & out   & core interrupt signal \\
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        \hline
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        \verb|calc_time| & 1     & out   & is high when core is performing a multiplication, for monitoring \\
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        \hline
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\end{tabular}%
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\newline \newline
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\textbf{Note 1:} The function and timing of this signal is defined in the IBM\textsuperscript{\textregistered} 128-Bit Processor Local Bus Architecture Specification
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Version 4.6.
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\section{Registers}
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This section specifies the IP core internal registers as seen from the software. These registers allow to control and
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configure the modular exponentiation core and to read out its state. All addresses given in this table are relative to the
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IP core's base address.\\
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\newline
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% Table generated by Excel2LaTeX
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\begin{tabular}{|l|c|c|c|l|}
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\hline
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\rowcolor{Gray}
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\textbf{Name} & \textbf{Width} & \textbf{Address} & \textbf{Access} & \textbf{Description} \bigstrut\\
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\hline
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control register                & 32 & 0x0000 & RW      & multiplier core control signals and \bigstrut[t]\\
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                                                &       &               &               & interrupt flags register\bigstrut[b]\\
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\hline
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software reset                  & 32 & 0x0100 & W       & soft reset for the IP core  \bigstrut\\
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\hline
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\multicolumn{5}{|l|}{\textbf{\textit{Interrupt controller registers}}} \bigstrut\\
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\hline
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global interrupt enable register        & 32 & 0x021C & RW & global interrupt enable for the IP core \bigstrut[t]\\
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interrupt status register                       & 32 & 0x0220 & R  & register for interrupt status flags\\
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interrupt enable register                       & 32 & 0x0228 & RW & register to enable individual IP core interrupts \bigstrut[b]\\
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\hline
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\end{tabular}%
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223
\newpage
224
\subsection{Control register (offset = 0x0000)}
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This registers holds the control inputs to the multiplier core and the interrupt flags.\\
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\begin{figure}[H]
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\centering
228
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_control_reg.pdf}
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\caption{control register}
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\end{figure}
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233
\begin{tabular}{ll}
234
bits 0-1        & P\_SEL : selects which pipeline part to be active\\
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                        & $\bullet$  "01" lower pipeline part\\
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                        & $\bullet$  "10" higher pipeline part\\
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                        & $\bullet$  "11" full pipeline\\
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                        & $\bullet$  "00" invalid selection\\
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                        &\\
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bits 2-3        & DEST\_OP : selects the operand (0-3) to store the result in for a single\\
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                        & Montgomery multiplication\footnotemark\\
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                        &\\
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bits 4-5        & X\_OP : selects the x operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
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                        &\\
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bits 6-7        & Y\_OP : selects the y operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
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                        &\\
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bit 8           & START : starts the multiplication/exponentiation\\
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                        &\\
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bit 9           & EXP/M : selects the operating mode\\
250
                        & $\bullet$  "0" single Montgomery multiplications\\
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                        & $\bullet$  "1" simultaneous exponentiations\\
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                        &\\
253
bits 10-15      & unimplemented\\
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                        &\\
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bit 16          & READY : ready flag, "1" when multiplication is done\\
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                        & must be cleared in software\\
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                        &\\
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bit 17          & MEM\_ERR : memory collision error flag, "1" when write error occurred\\
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                        & must be cleared in software\\
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                        &\\
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bit 18          & FIFO\_FULL : FIFO full error flag, "1" when FIFO is full\\
262
                        & must be cleared in software\\
263
                        &\\
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bit 19          & FIFO\_ERR : FIFO write/push error flag, "1" when push error occurred\\
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                        & must be cleared in software\\
266
                        &\\
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bits 20-31      & unimplemented\\
268
                        &\\
269
\end{tabular}
270
\newline
271
\newline
272
\footnotetext{when the core is running in exponentiation mode, the parameters DEST\_OP, X\_OP and Y\_OP have no effect.}
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274
\newpage
275
\subsection{Software reset register (offset = 0x0100)}
276
This is a register with write only access, and provides the possibility to reset the IP core from software by writing
277
0x0000000A to this address. The reset affects the full IP core, thus resetting the control register, interrupt controller,
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the multiplier pipeline, FIFO and control logic of the core.
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280
\subsection{Global interrupt enable register (offset = 0x021C)}
281
This register contains a single defined bit in the high-order position. The GIE bit enables or disables all interrupts
282
form the IP core.\\
283
\begin{figure}[H]
284
\centering
285
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_gie_reg.pdf}
286
\caption{Global interrupt enable register}
287
\end{figure}
288
 
289
\begin{tabular}{ll}
290
bit 0           & GIE : Global interrupt enable\\
291
                        & $\bullet$  "0" disables all core interrupts\\
292
                        & $\bullet$  "1" enables all core interrupts\\
293
                        &\\
294
bits 1-31       & unimplemented\\
295
                        &\\
296
\end{tabular}
297
 
298
\subsection{Interrupt status register (offset = 0x0220)}
299
Read-only register that contains the status of the core interrupts. Currently there is only one common interrupt from
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the core that is asserted when a multiplication/exponentiation is done, FIFO is full, on FIFO push error or memory write
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collision.\\
302
\begin{figure}[H]
303
\centering
304
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_is_reg.pdf}
305
\caption{Interrupt status register}
306
\end{figure}
307
 
308
\begin{tabular}{ll}
309
bits 0-30       & unimplemented\\
310
                        &\\
311
bit 31          & CIS : Core interrupt status\\
312
                        & is high when interrupt is requested from core\\
313
                        &\\
314
\end{tabular}
315
 
316
\subsection{interrupt enable register (offset = 0x0228)}
317
This register contains the interrupt enable bits for the respective interrupt bits of the interrupt status register.\\
318
\begin{figure}[H]
319
\centering
320
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_ie_reg.pdf}
321
\caption{Interrupt enable register}
322
\end{figure}
323
\begin{tabular}{ll}
324
bits 0-30       & unimplemented\\
325
                        &\\
326
bit 31          & CIE : Core interrupt enable\\
327
                        & $\bullet$  "0" disable core interrupt\\
328
                        & $\bullet$  "1" enable core interrupt\\
329
                        &\\
330
\end{tabular}
331
 
332
\section{Interfacing the core's RAM}
333
Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
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address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
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supported due to the structure of the RAM.
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337
\section{Handling interrupts}
338
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
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determine the source of the interrupt by reading out the interrupt flag of the control register.