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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b.vhd] - Blame information for rev 14

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----------------------------------------------------------------------  
----  cell_1b                                                      ---- 
----                                                              ---- 
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----  Description                                                 ---- 
----    1-bit cell for use in the montgommery multiplier systolic ----
----    array                                                     ----
----                                                              ---- 
----  Dependencies:                                               ---- 
----    - cell_1bit_adder                                         ---- 
----    - cell_1bit_mux                                           ----
----                                                              ----
----  Authors:                                                    ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
----                                                              ---- 
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- 1-bit cell for the systolic array
entity cell_1b is
  port (
    -- operand input bits (m+y, y and m)
    my   : in  std_logic;
    y    : in  std_logic;
    m    : in  std_logic;
    -- operand x input bit and q
    x    : in  std_logic;
    q    : in  std_logic;
    -- previous result input bit
    a    : in  std_logic;
    -- carry's
    cin  : in  std_logic;
    cout : out std_logic;
    -- cell result out
    r    : out std_logic
  );
end cell_1b;
 
 
architecture Structural of cell_1b is
  -- mux to adder connection
  signal mux2adder : std_logic;
begin
 
  -- mux for my, y and m input bits
  cell_mux : cell_1b_mux
  port map(
    my     => my,
    y      => y,
    m      => m,
    x      => x,
    q      => q,
    result => mux2adder
  );
 
  -- full adder for a+mux2adder
  cell_adder : cell_1b_adder
  port map(
    a    => a,
    b    => mux2adder,
    cin  => cin,
    cout => cout,
    r    => r
  );
 
end Structural;

Line No.	Rev	Author	Line
1	3	JonasDC	`----------------------------------------------------------------------`
2	14	JonasDC	`---- cell_1b ----`
3	3	JonasDC	`---- ----`
4			`---- This file is part of the ----`
5			`---- Modular Simultaneous Exponentiation Core project ----`
6			`---- http://www.opencores.org/cores/mod_sim_exp/ ----`
7			`---- ----`
8			`---- Description ----`
9	9	JonasDC	`---- 1-bit cell for use in the montgommery multiplier systolic ----`
10	3	JonasDC	`---- array ----`
11			`---- ----`
12			`---- Dependencies: ----`
13			`---- - cell_1bit_adder ----`
14			`---- - cell_1bit_mux ----`
15			`---- ----`
16			`---- Authors: ----`
17			`---- - Geoffrey Ottoy, DraMCo research group ----`
18			`---- - Jonas De Craene, JonasDC@opencores.org ----`
19			`---- ----`
20			`----------------------------------------------------------------------`
21			`---- ----`
22			`---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----`
23			`---- ----`
24			`---- This source file may be used and distributed without ----`
25			`---- restriction provided that this copyright statement is not ----`
26			`---- removed from the file and that any derivative work contains ----`
27			`---- the original copyright notice and the associated disclaimer. ----`
28			`---- ----`
29			`---- This source file is free software; you can redistribute it ----`
30			`---- and/or modify it under the terms of the GNU Lesser General ----`
31			`---- Public License as published by the Free Software Foundation; ----`
32			`---- either version 2.1 of the License, or (at your option) any ----`
33			`---- later version. ----`
34			`---- ----`
35			`---- This source is distributed in the hope that it will be ----`
36			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
37			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
38			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
39			`---- details. ----`
40			`---- ----`
41			`---- You should have received a copy of the GNU Lesser General ----`
42			`---- Public License along with this source; if not, download it ----`
43			`---- from http://www.opencores.org/lgpl.shtml ----`
44			`---- ----`
45			`----------------------------------------------------------------------`
46	2	JonasDC
47	3	JonasDC	`library ieee;`
48			`use ieee.std_logic_1164.all;`
49			`use ieee.std_logic_arith.all;`
50			`use ieee.std_logic_unsigned.all;`
51	2	JonasDC
52	3	JonasDC	`library mod_sim_exp;`
53			`use mod_sim_exp.mod_sim_exp_pkg.all;`
54
55	9	JonasDC	`-- 1-bit cell for the systolic array`
56	2	JonasDC	`entity cell_1b is`
57	3	JonasDC	`port (`
58	9	JonasDC	`-- operand input bits (m+y, y and m)`
59	3	JonasDC	`my : in std_logic;`
60			`y : in std_logic;`
61			`m : in std_logic;`
62	14	JonasDC	`-- operand x input bit and q`
63	3	JonasDC	`x : in std_logic;`
64			`q : in std_logic;`
65	9	JonasDC	`-- previous result input bit`
66	3	JonasDC	`a : in std_logic;`
67	9	JonasDC	`-- carry's`
68	3	JonasDC	`cin : in std_logic;`
69			`cout : out std_logic;`
70	9	JonasDC	`-- cell result out`
71	3	JonasDC	`r : out std_logic`
72			`);`
73	2	JonasDC	`end cell_1b;`
74
75	3	JonasDC
76	2	JonasDC	`architecture Structural of cell_1b is`
77	9	JonasDC	`-- mux to adder connection`
78	3	JonasDC	`signal mux2adder : std_logic;`
79	2	JonasDC	`begin`
80	9	JonasDC
81			`-- mux for my, y and m input bits`
82	3	JonasDC	`cell_mux : cell_1b_mux`
83			`port map(`
84			`my => my,`
85			`y => y,`
86			`m => m,`
87			`x => x,`
88			`q => q,`
89			`result => mux2adder`
90			`);`
91	9	JonasDC
92			`-- full adder for a+mux2adder`
93	3	JonasDC	`cell_adder : cell_1b_adder`
94			`port map(`
95	9	JonasDC	`a => a,`
96			`b => mux2adder,`
97			`cin => cin,`
98			`cout => cout,`
99			`r => r`
100	3	JonasDC	`);`
101
102			`end Structural;`

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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b.vhd] - Blame information for rev 14