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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [clk_sync.vhd] - Blame information for rev 94

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1 94 JonasDC
----------------------------------------------------------------------  
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----  clk_sync                                                    ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    synchronises signal A to clock B, avoiding metastable     ----
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----    states.                                                   ----
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----                                                              ---- 
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----  Dependencies: none                                          ---- 
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----                                                              ---- 
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity clk_sync is
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  port (
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    sigA : in std_logic;
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    clkB : in std_logic;
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    sigB : out std_logic
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  );
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end clk_sync;
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architecture arch of clk_sync is
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  signal sigMeta : std_logic; -- signal where metastable states are possible
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begin
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  sync : process (clkB)
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  begin
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    if rising_edge(clkB) then
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      sigMeta <= sigA;
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      sigB <= sigMeta;
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    end if;
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  end process;
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end arch;

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