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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Blame information for rev 63

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----------------------------------------------------------------------  
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----  mod_sim_exp_core                                            ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    toplevel of a modular simultaneous exponentiation core    ----
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----    using a pipelined montgommery multiplier with split       ----
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----    pipeline and auto-run support                             ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - mont_mult_sys_pipeline                                  ----
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----    - operand_mem                                             ----
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----    - fifo_primitive                                          ----
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----    - mont_ctrl                                               ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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-- toplevel of the modular simultaneous exponentiation core
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-- contains an operand and modulus ram, multiplier, an exponent fifo
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-- and control logic
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entity mod_sim_exp_core is
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  generic(
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    C_NR_BITS_TOTAL   : integer := 1536;
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    C_NR_STAGES_TOTAL : integer := 96;
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    C_NR_STAGES_LOW   : integer := 32;
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    C_SPLIT_PIPELINE  : boolean := true;
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    C_NR_OP           : integer := 4;
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    C_NR_M            : integer := 2;
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    C_FIFO_DEPTH      : integer := 32
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  );
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  port(
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    clk   : in  std_logic;
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    reset : in  std_logic;
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      -- operand memory interface (plb shared memory)
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    write_enable : in  std_logic; -- write data to operand ram
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    data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
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    rw_address   : in  std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0);   -- operand ram address bus
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    data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
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    collision    : out std_logic; -- write collision
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      -- op_sel fifo interface
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    fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
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    fifo_push   : in  std_logic;  -- push data in exponent fifo
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    fifo_full   : out std_logic;  -- high if fifo is full
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    fifo_nopush : out std_logic;  -- high if error during push
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      -- control signals
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    start          : in  std_logic; -- start multiplication/exponentiation
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    exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
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    ready          : out std_logic; -- calculations done
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    x_sel_single   : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
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    y_sel_single   : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
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    dest_op_single : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
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    p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
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    calc_time      : out std_logic;
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    modulus_sel    : in std_logic_vector(log2(C_NR_M)-1 downto 0)
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  );
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end mod_sim_exp_core;
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architecture Structural of mod_sim_exp_core is
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  -- data busses
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  signal xy   : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- x and y operand data bus RAM -> multiplier
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  signal m    : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- modulus data bus RAM -> multiplier
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  signal r    : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- result data bus RAM <- multiplier
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  -- control signals
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  signal op_sel           : std_logic_vector(1 downto 0); -- operand selection 
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  signal result_dest_op   : std_logic_vector(1 downto 0); -- result destination operand
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  signal mult_ready       : std_logic;
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  signal start_mult       : std_logic;
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  signal load_x         : std_logic;
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  signal load_result      : std_logic;
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  -- fifo signals
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  signal fifo_empty : std_logic;
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  signal fifo_pop   : std_logic;
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  signal fifo_nopop : std_logic;
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  signal fifo_dout  : std_logic_vector(31 downto 0);
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begin
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  -- The actual multiplier
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  the_multiplier : mont_multiplier
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  generic map(
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    n  => C_NR_BITS_TOTAL,
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    t  => C_NR_STAGES_TOTAL,
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    tl => C_NR_STAGES_LOW,
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    split => C_SPLIT_PIPELINE
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  )
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  port map(
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    core_clk => clk,
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    xy       => xy,
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    m        => m,
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    r        => r,
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    start    => start_mult,
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    reset    => reset,
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    p_sel    => p_sel,
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    load_x   => load_x,
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    ready    => mult_ready
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  );
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  -- Block ram memory for storing the operands and the modulus
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  the_memory : operand_mem_gen
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  generic map(
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    width => C_NR_BITS_TOTAL,
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    nr_op => C_NR_OP,
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    nr_m  => C_NR_M
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  )
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  port map(
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    data_in        => data_in,
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    data_out       => data_out,
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    rw_address     => rw_address,
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    write_enable   => write_enable,
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    op_sel         => op_sel,
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    xy_out         => xy,
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    m              => m,
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    result_in      => r,
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    load_result    => load_result,
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    result_dest_op => result_dest_op,
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    collision      => collision,
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    clk            => clk,
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    modulus_sel     => modulus_sel
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  );
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        result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
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  -- A fifo for auto-run operand selection
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  the_exponent_fifo : fifo_generic
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  generic map(
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    depth => C_FIFO_DEPTH
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  )
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  port map(
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    clk    => clk,
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    din    => fifo_din,
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    dout   => fifo_dout,
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    empty  => fifo_empty,
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    full   => fifo_full,
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    push   => fifo_push,
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    pop    => fifo_pop,
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    reset  => reset,
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    nopop  => fifo_nopop,
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    nopush => fifo_nopush
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  );
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  -- The control logic for the core
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  the_control_unit : mont_ctrl
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  port map(
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    clk              => clk,
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    reset            => reset,
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    start            => start,
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    x_sel_single     => x_sel_single,
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    y_sel_single     => y_sel_single,
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    run_auto         => exp_m,
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    op_buffer_empty  => fifo_empty,
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    op_sel_buffer    => fifo_dout,
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    read_buffer      => fifo_pop,
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    done             => ready,
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    calc_time        => calc_time,
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    op_sel           => op_sel,
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    load_x           => load_x,
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    load_result      => load_result,
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    start_multiplier => start_mult,
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    multiplier_ready => mult_ready
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  );
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end Structural;

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