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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52
 
53 16 JonasDC
  --------------------------------------------------------------------
54
  -- d_flip_flop
55
  --------------------------------------------------------------------
56
  --    1-bit D flip-flop with asynchronous active high reset
57
  -- 
58 9 JonasDC
  component d_flip_flop is
59
    port(
60
      core_clk : in  std_logic; -- clock signal
61
      reset    : in  std_logic; -- active high reset
62
      din      : in  std_logic; -- data in
63
      dout     : out std_logic  -- data out
64 3 JonasDC
    );
65 9 JonasDC
  end component d_flip_flop;
66
 
67 16 JonasDC
  --------------------------------------------------------------------
68
  -- register_1b
69
  --------------------------------------------------------------------
70
  --    1-bit register with asynchronous reset and clock enable
71
  -- 
72 9 JonasDC
  component register_1b is
73
    port(
74
      core_clk : in  std_logic; -- clock input
75
      ce       : in  std_logic; -- clock enable (active high)
76
      reset    : in  std_logic; -- reset (active high)
77
      din      : in  std_logic; -- data in
78
      dout     : out std_logic  -- data out
79 3 JonasDC
    );
80 9 JonasDC
  end component register_1b;
81 3 JonasDC
 
82 16 JonasDC
  --------------------------------------------------------------------
83
  -- register_n
84
  --------------------------------------------------------------------
85
  --    n-bit register with asynchronous reset and clock enable
86
  -- 
87 9 JonasDC
  component register_n is
88
    generic(
89 16 JonasDC
      width : integer := 4
90 3 JonasDC
    );
91 9 JonasDC
    port(
92
      core_clk : in  std_logic; -- clock input
93
      ce       : in  std_logic; -- clock enable (active high)
94
      reset    : in  std_logic; -- reset (active high)
95 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
96
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
97 3 JonasDC
    );
98 9 JonasDC
  end component register_n;
99 3 JonasDC
 
100 16 JonasDC
  --------------------------------------------------------------------
101
  -- cell_1b_adder
102
  --------------------------------------------------------------------
103
  --    1-bit full adder cell using combinatorial logic
104
  --    
105 3 JonasDC
  component cell_1b_adder is
106
    port (
107 9 JonasDC
      -- input operands a, b
108
      a    : in  std_logic;
109
      b    : in  std_logic;
110
      -- carry in, out
111
      cin  : in  std_logic;
112
      cout : out  std_logic;
113
      -- result out
114
      r    : out  std_logic
115 3 JonasDC
    );
116
  end component cell_1b_adder;
117
 
118 16 JonasDC
  --------------------------------------------------------------------
119
  -- cell_1b_mux
120
  --------------------------------------------------------------------
121
  --    1-bit mux for a standard cell in the montgommery multiplier 
122
  --    systolic array
123
  -- 
124 3 JonasDC
  component cell_1b_mux is
125
    port (
126 9 JonasDC
      -- input bits
127
      my     : in  std_logic;
128 3 JonasDC
      y      : in  std_logic;
129
      m      : in  std_logic;
130 9 JonasDC
      -- selection bits
131 3 JonasDC
      x      : in  std_logic;
132
      q      : in  std_logic;
133 9 JonasDC
      -- mux out
134 3 JonasDC
      result : out std_logic
135
    );
136
  end component cell_1b_mux;
137
 
138 16 JonasDC
  --------------------------------------------------------------------
139
  -- cell_1b
140
  --------------------------------------------------------------------
141
  --    1-bit cell for the systolic array
142
  -- 
143 3 JonasDC
  component cell_1b is
144
    port (
145 9 JonasDC
      -- operand input bits (m+y, y and m)
146 3 JonasDC
      my   : in  std_logic;
147
      y    : in  std_logic;
148
      m    : in  std_logic;
149 16 JonasDC
      -- operand x input bit and q
150 3 JonasDC
      x    : in  std_logic;
151
      q    : in  std_logic;
152 9 JonasDC
      -- previous result input bit
153 3 JonasDC
      a    : in  std_logic;
154 9 JonasDC
      -- carry's
155 3 JonasDC
      cin  : in  std_logic;
156
      cout : out std_logic;
157 9 JonasDC
      -- cell result out
158 3 JonasDC
      r    : out std_logic
159
    );
160
  end component cell_1b;
161
 
162 16 JonasDC
  --------------------------------------------------------------------
163
  -- adder_block
164
  --------------------------------------------------------------------
165
  --    (width)-bit full adder block using cell_1b_adders with buffered
166
  --    carry out
167
  -- 
168 9 JonasDC
  component adder_block is
169
    generic (
170
      width : integer := 32 --adder operand widths
171
    );
172
    port (
173
      -- clock input
174
      core_clk : in std_logic;
175
      -- adder input operands a, b (width)-bit
176
      a : in std_logic_vector((width-1) downto 0);
177
      b : in std_logic_vector((width-1) downto 0);
178
      -- carry in, out
179
      cin   : in std_logic;
180
      cout  : out std_logic;
181
      -- adder result out (width)-bit
182
      r : out std_logic_vector((width-1) downto 0)
183
    );
184
  end component adder_block;
185
 
186 16 JonasDC
  --------------------------------------------------------------------
187
  -- adder_n
188
  --------------------------------------------------------------------
189
  --    n-bit adder using adder blocks. works in stages, to prevent 
190
  --    large carry propagation. 
191
  --    Result avaiable after (width/block_width) clock cycles
192
  -- 
193 9 JonasDC
  component adder_n is
194
    generic (
195
      width       : integer := 1536; -- adder operands width
196
      block_width : integer := 8     -- adder blocks size
197
    );
198
    port (
199
      -- clock input
200
      core_clk : in std_logic;
201
      -- adder input operands (width)-bit
202
      a : in std_logic_vector((width-1) downto 0);
203
      b : in std_logic_vector((width-1) downto 0);
204
      -- carry in, out
205
      cin   : in std_logic;
206
      cout  : out std_logic;
207
      -- adder output result (width)-bit
208
      r : out std_logic_vector((width-1) downto 0)
209
    );
210
  end component adder_n;
211
 
212
  component autorun_cntrl is
213
    port (
214
      clk              : in  std_logic;
215
      reset            : in  std_logic;
216
      start            : in  std_logic;
217
      done             : out  std_logic;
218
      op_sel           : out  std_logic_vector (1 downto 0);
219
      start_multiplier : out  std_logic;
220
      multiplier_done  : in  std_logic;
221
      read_buffer      : out  std_logic;
222
      buffer_din       : in  std_logic_vector (31 downto 0);
223
      buffer_empty     : in  std_logic
224
    );
225
  end component autorun_cntrl;
226
 
227 3 JonasDC
  component counter_sync is
228
    generic(
229
      max_value : integer := 1024
230
    );
231
    port(
232
      reset_value : in integer;
233
      core_clk    : in std_logic;
234
      ce          : in std_logic;
235
      reset       : in std_logic;
236
      overflow    : out std_logic
237
    );
238
  end component counter_sync;
239
 
240
  component fifo_primitive is
241
    port (
242
      clk    : in  std_logic;
243
      din    : in  std_logic_vector (31 downto 0);
244
      dout   : out  std_logic_vector (31 downto 0);
245
      empty  : out  std_logic;
246
      full   : out  std_logic;
247
      push   : in  std_logic;
248
      pop    : in  std_logic;
249
      reset  : in std_logic;
250
      nopop  : out std_logic;
251
      nopush : out std_logic
252
    );
253
  end component fifo_primitive;
254
 
255
  component first_stage is
256
    generic(
257
      width : integer := 16 -- must be the same as width of the standard stage
258
    );
259
    port(
260
      core_clk : in  std_logic;
261
      my       : in  std_logic_vector((width) downto 0);
262
      y        : in  std_logic_vector((width) downto 0);
263
      m        : in  std_logic_vector((width) downto 0);
264
      xin      : in  std_logic;
265
      xout     : out std_logic;
266
      qout     : out std_logic;
267
      a_msb    : in  std_logic;
268
      cout     : out std_logic;
269
      start    : in  std_logic;
270
      reset    : in  std_logic;
271
      done     : out std_logic;
272
      r        : out std_logic_vector((width-1) downto 0)
273
    );
274
  end component first_stage;
275
 
276
  component last_stage is
277
    generic(
278
      width : integer := 16 -- must be the same as width of the standard stage
279
    );
280
    port(
281
      core_clk : in  std_logic;
282
      my       : in  std_logic_vector((width-1) downto 0);
283
      y        : in  std_logic_vector((width-2) downto 0);
284
      m        : in  std_logic_vector((width-2) downto 0);
285
      xin      : in  std_logic;
286
      qin      : in  std_logic;
287
      cin      : in  std_logic;
288
      start    : in  std_logic;
289
      reset    : in  std_logic;
290
      r        : out std_logic_vector((width+1) downto 0)
291
    );
292
  end component last_stage;
293
 
294
  component modulus_ram is
295
    port(
296
      clk           : in std_logic;
297
      modulus_addr  : in std_logic_vector(5 downto 0);
298
      write_modulus : in std_logic;
299
      modulus_in    : in std_logic_vector(31 downto 0);
300
      modulus_out   : out std_logic_vector(1535 downto 0)
301
    );
302
  end component modulus_ram;
303
 
304
  component mont_ctrl is
305
    port (
306
      clk   : in std_logic;
307
      reset : in std_logic;
308
        -- bus side
309
      start           : in std_logic;
310
      x_sel_single    : in std_logic_vector(1 downto 0);
311
      y_sel_single    : in std_logic_vector(1 downto 0);
312
      run_auto        : in std_logic;
313
      op_buffer_empty : in std_logic;
314
      op_sel_buffer   : in std_logic_vector(31 downto 0);
315
      read_buffer     : out std_logic;
316
      buffer_noread   : in std_logic;
317
      done            : out std_logic;
318
      calc_time       : out std_logic;
319
        -- multiplier side
320
      op_sel           : out std_logic_vector(1 downto 0);
321
      load_x           : out std_logic;
322
      load_result      : out std_logic;
323
      start_multiplier : out std_logic;
324
      multiplier_ready : in std_logic
325
    );
326
  end component mont_ctrl;
327
 
328
  component mont_mult_sys_pipeline is
329
    generic (
330
      n          : integer := 1536;
331
      nr_stages  : integer := 96; --(divides n, bits_low & (n-bits_low))
332
      stages_low : integer := 32
333
    );
334
    port (
335
      core_clk : in std_logic;
336
      xy       : in std_logic_vector((n-1) downto 0);
337
      m        : in std_logic_vector((n-1) downto 0);
338
      r        : out std_logic_vector((n-1) downto 0);
339
      start    : in std_logic;
340
      reset    : in std_logic;
341
      p_sel    : in std_logic_vector(1 downto 0);
342
      load_x   : in std_logic;
343
      ready    : out std_logic
344
    );
345
  end component mont_mult_sys_pipeline;
346
 
347
  component multiplier_core is
348
    port(
349
      clk   : in  std_logic;
350
      reset : in  std_logic;
351
        -- operand memory interface (plb shared memory)
352
      write_enable : in  std_logic;
353
      data_in      : in  std_logic_vector (31 downto 0);
354
      rw_address   : in  std_logic_vector (8 downto 0);
355
      data_out     : out std_logic_vector (31 downto 0);
356
      collision    : out std_logic;
357
        -- op_sel fifo interface
358
      fifo_din    : in  std_logic_vector (31 downto 0);
359
      fifo_push   : in  std_logic;
360
      fifo_full   : out std_logic;
361
      fifo_nopush : out std_logic;
362
        -- ctrl signals
363
      start          : in  std_logic;
364
      run_auto       : in  std_logic;
365
      ready          : out std_logic;
366
      x_sel_single   : in  std_logic_vector (1 downto 0);
367
      y_sel_single   : in  std_logic_vector (1 downto 0);
368
      dest_op_single : in  std_logic_vector (1 downto 0);
369
      p_sel          : in  std_logic_vector (1 downto 0);
370
      calc_time      : out std_logic
371
    );
372
  end component multiplier_core;
373
 
374
  component operand_dp is
375
    port (
376
      clka  : in std_logic;
377
      wea   : in std_logic_vector(0 downto 0);
378
      addra : in std_logic_vector(5 downto 0);
379
      dina  : in std_logic_vector(31 downto 0);
380
      douta : out std_logic_vector(511 downto 0);
381
      clkb  : in std_logic;
382
      web   : in std_logic_vector(0 downto 0);
383
      addrb : in std_logic_vector(5 downto 0);
384
      dinb  : in std_logic_vector(511 downto 0);
385
      doutb : out std_logic_vector(31 downto 0)
386
    );
387
  end component operand_dp;
388
 
389
  component operand_mem is
390
    generic(n : integer := 1536
391
    );
392
    port(
393
        -- data interface (plb side)
394
      data_in    : in  std_logic_vector(31 downto 0);
395
      data_out   : out  std_logic_vector(31 downto 0);
396
      rw_address : in  std_logic_vector(8 downto 0);
397
        -- address structure:
398
        -- bit:  8   -> '1': modulus
399
        --              '0': operands
400
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
401
        --              don't care in case of modulus
402
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
403
 
404
        -- operand interface (multiplier side)
405
      op_sel    : in  std_logic_vector(1 downto 0);
406
      xy_out    : out  std_logic_vector(1535 downto 0);
407
      m         : out  std_logic_vector(1535 downto 0);
408
      result_in : in std_logic_vector(1535 downto 0);
409
        -- control signals
410
      load_op        : in std_logic;
411
      load_m         : in std_logic;
412
      load_result    : in std_logic;
413
      result_dest_op : in std_logic_vector(1 downto 0);
414
      collision      : out std_logic;
415
        -- system clock
416
      clk : in  std_logic
417
    );
418
  end component operand_mem;
419
 
420
  component operand_ram is
421
    port( -- write_operand_ack voorzien?
422
      -- global ports
423
      clk       : in std_logic;
424
      collision : out std_logic;
425
      -- bus side connections (32-bit serial)
426
      operand_addr   : in std_logic_vector(5 downto 0);
427
      operand_in     : in std_logic_vector(31 downto 0);
428
      operand_in_sel : in std_logic_vector(1 downto 0);
429
      result_out     : out std_logic_vector(31 downto 0);
430
      write_operand  : in std_logic;
431
      -- multiplier side connections (1536 bit parallel)
432
      result_dest_op  : in std_logic_vector(1 downto 0);
433
      operand_out     : out std_logic_vector(1535 downto 0);
434
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
435
      write_result    : in std_logic;
436
      result_in       : in std_logic_vector(1535 downto 0)
437
    );
438
  end component operand_ram;
439
 
440
  component operands_sp is
441
    port (
442
      clka  : in std_logic;
443
      wea   : in std_logic_vector(0 downto 0);
444
      addra : in std_logic_vector(4 downto 0);
445
      dina  : in std_logic_vector(31 downto 0);
446
      douta : out std_logic_vector(511 downto 0)
447
    );
448
  end component operands_sp;
449
 
450
  component standard_cell_block is
451
    generic (
452
      width : integer := 16
453
    );
454
    port (
455
      my   : in  std_logic_vector((width-1) downto 0);
456
      y    : in  std_logic_vector((width-1) downto 0);
457
      m    : in  std_logic_vector((width-1) downto 0);
458
      x    : in  std_logic;
459
      q    : in  std_logic;
460
      a    : in  std_logic_vector((width-1) downto 0);
461
      cin  : in std_logic;
462
      cout : out std_logic;
463
      r    : out  std_logic_vector((width-1) downto 0)
464
    );
465
  end component standard_cell_block;
466
 
467
  component standard_stage is
468
    generic(
469
      width : integer := 32
470
    );
471
    port(
472
      core_clk : in  std_logic;
473
      my       : in  std_logic_vector((width-1) downto 0);
474
      y        : in  std_logic_vector((width-1) downto 0);
475
      m        : in  std_logic_vector((width-1) downto 0);
476
      xin      : in  std_logic;
477
      qin      : in  std_logic;
478
      xout     : out std_logic;
479
      qout     : out std_logic;
480
      a_msb    : in  std_logic;
481
      cin      : in  std_logic;
482
      cout     : out std_logic;
483
      start    : in  std_logic;
484
      reset    : in  std_logic;
485
      done : out std_logic;
486
      r    : out std_logic_vector((width-1) downto 0)
487
    );
488
  end component standard_stage;
489
 
490
  component stepping_logic is
491
    generic(
492
      n : integer := 1536; -- max nr of steps required to complete a multiplication
493
      t : integer := 192 -- total nr of steps in the pipeline
494
    );
495
    port(
496
      core_clk          : in  std_logic;
497
      start             : in  std_logic;
498
      reset             : in  std_logic;
499
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
500
      n_sel             : in integer range 0 to n; -- nr of steps required for a complete multiplication
501
      start_first_stage : out std_logic;
502
      stepping_done     : out std_logic
503
    );
504
  end component stepping_logic;
505
 
506
  component systolic_pipeline is
507
    generic(
508
      n  : integer := 1536; -- width of the operands (# bits)
509
      t  : integer := 192;  -- number of stages (divider of n) >= 2
510
      tl : integer := 64    -- best take t = sqrt(n)
511
    );
512
    port(
513
      core_clk : in  std_logic;
514
      my       : in  std_logic_vector((n) downto 0);
515
      y        : in  std_logic_vector((n-1) downto 0);
516
      m        : in  std_logic_vector((n-1) downto 0);
517
      xi       : in  std_logic;
518
      start    : in  std_logic;
519
      reset    : in  std_logic;
520
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
521
      ready    : out std_logic;
522
      next_x   : out std_logic;
523
      r        : out std_logic_vector((n+1) downto 0)
524
    );
525
  end component systolic_pipeline;
526
 
527
  component x_shift_reg is
528
    generic(
529
      n  : integer := 1536;
530
      t  : integer := 48;
531
      tl : integer := 16
532
    );
533
    port(
534
      clk    : in  std_logic;
535
      reset  : in  std_logic;
536
      x_in   : in  std_logic_vector((n-1) downto 0);
537
      load_x : in  std_logic;
538
      next_x : in  std_logic;
539
      p_sel  : in  std_logic_vector(1 downto 0);
540
      x_i    : out std_logic
541
    );
542
  end component x_shift_reg;
543
 
544
end package mod_sim_exp_pkg;

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