OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Blame information for rev 17

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52
 
53 16 JonasDC
  --------------------------------------------------------------------
54
  -- d_flip_flop
55
  --------------------------------------------------------------------
56
  --    1-bit D flip-flop with asynchronous active high reset
57
  -- 
58 9 JonasDC
  component d_flip_flop is
59
    port(
60
      core_clk : in  std_logic; -- clock signal
61
      reset    : in  std_logic; -- active high reset
62
      din      : in  std_logic; -- data in
63
      dout     : out std_logic  -- data out
64 3 JonasDC
    );
65 9 JonasDC
  end component d_flip_flop;
66
 
67 16 JonasDC
  --------------------------------------------------------------------
68
  -- register_1b
69
  --------------------------------------------------------------------
70
  --    1-bit register with asynchronous reset and clock enable
71
  -- 
72 9 JonasDC
  component register_1b is
73
    port(
74
      core_clk : in  std_logic; -- clock input
75
      ce       : in  std_logic; -- clock enable (active high)
76
      reset    : in  std_logic; -- reset (active high)
77
      din      : in  std_logic; -- data in
78
      dout     : out std_logic  -- data out
79 3 JonasDC
    );
80 9 JonasDC
  end component register_1b;
81 3 JonasDC
 
82 16 JonasDC
  --------------------------------------------------------------------
83
  -- register_n
84
  --------------------------------------------------------------------
85
  --    n-bit register with asynchronous reset and clock enable
86
  -- 
87 9 JonasDC
  component register_n is
88
    generic(
89 16 JonasDC
      width : integer := 4
90 3 JonasDC
    );
91 9 JonasDC
    port(
92
      core_clk : in  std_logic; -- clock input
93
      ce       : in  std_logic; -- clock enable (active high)
94
      reset    : in  std_logic; -- reset (active high)
95 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
96
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
97 3 JonasDC
    );
98 9 JonasDC
  end component register_n;
99 3 JonasDC
 
100 16 JonasDC
  --------------------------------------------------------------------
101
  -- cell_1b_adder
102
  --------------------------------------------------------------------
103
  --    1-bit full adder cell using combinatorial logic
104
  --    
105 3 JonasDC
  component cell_1b_adder is
106
    port (
107 9 JonasDC
      -- input operands a, b
108
      a    : in  std_logic;
109
      b    : in  std_logic;
110
      -- carry in, out
111
      cin  : in  std_logic;
112
      cout : out  std_logic;
113
      -- result out
114
      r    : out  std_logic
115 3 JonasDC
    );
116
  end component cell_1b_adder;
117
 
118 16 JonasDC
  --------------------------------------------------------------------
119
  -- cell_1b_mux
120
  --------------------------------------------------------------------
121
  --    1-bit mux for a standard cell in the montgommery multiplier 
122
  --    systolic array
123
  -- 
124 3 JonasDC
  component cell_1b_mux is
125
    port (
126 9 JonasDC
      -- input bits
127
      my     : in  std_logic;
128 3 JonasDC
      y      : in  std_logic;
129
      m      : in  std_logic;
130 9 JonasDC
      -- selection bits
131 3 JonasDC
      x      : in  std_logic;
132
      q      : in  std_logic;
133 9 JonasDC
      -- mux out
134 3 JonasDC
      result : out std_logic
135
    );
136
  end component cell_1b_mux;
137
 
138 16 JonasDC
  --------------------------------------------------------------------
139
  -- cell_1b
140
  --------------------------------------------------------------------
141
  --    1-bit cell for the systolic array
142
  -- 
143 3 JonasDC
  component cell_1b is
144
    port (
145 9 JonasDC
      -- operand input bits (m+y, y and m)
146 3 JonasDC
      my   : in  std_logic;
147
      y    : in  std_logic;
148
      m    : in  std_logic;
149 16 JonasDC
      -- operand x input bit and q
150 3 JonasDC
      x    : in  std_logic;
151
      q    : in  std_logic;
152 9 JonasDC
      -- previous result input bit
153 3 JonasDC
      a    : in  std_logic;
154 9 JonasDC
      -- carry's
155 3 JonasDC
      cin  : in  std_logic;
156
      cout : out std_logic;
157 9 JonasDC
      -- cell result out
158 3 JonasDC
      r    : out std_logic
159
    );
160
  end component cell_1b;
161
 
162 16 JonasDC
  --------------------------------------------------------------------
163
  -- adder_block
164
  --------------------------------------------------------------------
165
  --    (width)-bit full adder block using cell_1b_adders with buffered
166
  --    carry out
167
  -- 
168 9 JonasDC
  component adder_block is
169
    generic (
170
      width : integer := 32 --adder operand widths
171
    );
172
    port (
173
      -- clock input
174
      core_clk : in std_logic;
175
      -- adder input operands a, b (width)-bit
176
      a : in std_logic_vector((width-1) downto 0);
177
      b : in std_logic_vector((width-1) downto 0);
178
      -- carry in, out
179
      cin   : in std_logic;
180
      cout  : out std_logic;
181
      -- adder result out (width)-bit
182
      r : out std_logic_vector((width-1) downto 0)
183
    );
184
  end component adder_block;
185
 
186 16 JonasDC
  --------------------------------------------------------------------
187
  -- adder_n
188
  --------------------------------------------------------------------
189
  --    n-bit adder using adder blocks. works in stages, to prevent 
190
  --    large carry propagation. 
191
  --    Result avaiable after (width/block_width) clock cycles
192
  -- 
193 9 JonasDC
  component adder_n is
194
    generic (
195
      width       : integer := 1536; -- adder operands width
196
      block_width : integer := 8     -- adder blocks size
197
    );
198
    port (
199
      -- clock input
200
      core_clk : in std_logic;
201
      -- adder input operands (width)-bit
202
      a : in std_logic_vector((width-1) downto 0);
203
      b : in std_logic_vector((width-1) downto 0);
204
      -- carry in, out
205
      cin   : in std_logic;
206
      cout  : out std_logic;
207
      -- adder output result (width)-bit
208
      r : out std_logic_vector((width-1) downto 0)
209
    );
210
  end component adder_n;
211
 
212 17 JonasDC
  --------------------------------------------------------------------
213
  -- standard_cell_block
214
  --------------------------------------------------------------------
215
  --    a standard cell block of (width)-bit for the montgommery multiplier 
216
  --    systolic array
217
  -- 
218
  component standard_cell_block is
219
    generic (
220
      width : integer := 16
221
    );
222
    port (
223
      -- modulus and y operand input (width)-bit
224
      my   : in  std_logic_vector((width-1) downto 0);
225
      y    : in  std_logic_vector((width-1) downto 0);
226
      m    : in  std_logic_vector((width-1) downto 0);
227
      -- q and x operand input (serial input)
228
      x    : in  std_logic;
229
      q    : in  std_logic;
230
      -- previous result in (width)-bit
231
      a    : in  std_logic_vector((width-1) downto 0);
232
      -- carry in and out
233
      cin  : in std_logic;
234
      cout : out std_logic;
235
      -- result out (width)-bit
236
      r    : out  std_logic_vector((width-1) downto 0)
237
    );
238
  end component standard_cell_block;
239
 
240
  --------------------------------------------------------------------
241
  -- standard_stage
242
  --------------------------------------------------------------------
243
  --    standard stage for use in the montgommery multiplier pipeline
244
  --    the result is available after 1 clock cycle
245
  -- 
246
  component standard_stage is
247
    generic(
248
      width : integer := 32
249
    );
250
    port(
251
      -- clock input
252
      core_clk : in  std_logic;
253
      -- modulus and y operand input (width)-bit
254
      my       : in  std_logic_vector((width-1) downto 0);
255
      y        : in  std_logic_vector((width-1) downto 0);
256
      m        : in  std_logic_vector((width-1) downto 0);
257
      -- q and x operand input (serial input)
258
      xin      : in  std_logic;
259
      qin      : in  std_logic;
260
      -- q and x operand output (serial output)
261
      xout     : out std_logic;
262
      qout     : out std_logic;
263
      -- msb input (lsb from next stage, for shift right operation)
264
      a_msb    : in  std_logic;
265
      -- carry out(clocked) and in
266
      cin      : in  std_logic;
267
      cout     : out std_logic;
268
      -- control singals
269
      start    : in  std_logic;
270
      reset    : in  std_logic;
271
      done : out std_logic;
272
      -- result out
273
      r    : out std_logic_vector((width-1) downto 0)
274
    );
275
  end component standard_stage;
276
 
277 9 JonasDC
  component autorun_cntrl is
278
    port (
279
      clk              : in  std_logic;
280
      reset            : in  std_logic;
281
      start            : in  std_logic;
282
      done             : out  std_logic;
283
      op_sel           : out  std_logic_vector (1 downto 0);
284
      start_multiplier : out  std_logic;
285
      multiplier_done  : in  std_logic;
286
      read_buffer      : out  std_logic;
287
      buffer_din       : in  std_logic_vector (31 downto 0);
288
      buffer_empty     : in  std_logic
289
    );
290
  end component autorun_cntrl;
291
 
292 3 JonasDC
  component counter_sync is
293
    generic(
294
      max_value : integer := 1024
295
    );
296
    port(
297
      reset_value : in integer;
298
      core_clk    : in std_logic;
299
      ce          : in std_logic;
300
      reset       : in std_logic;
301
      overflow    : out std_logic
302
    );
303
  end component counter_sync;
304
 
305
  component fifo_primitive is
306
    port (
307
      clk    : in  std_logic;
308
      din    : in  std_logic_vector (31 downto 0);
309
      dout   : out  std_logic_vector (31 downto 0);
310
      empty  : out  std_logic;
311
      full   : out  std_logic;
312
      push   : in  std_logic;
313
      pop    : in  std_logic;
314
      reset  : in std_logic;
315
      nopop  : out std_logic;
316
      nopush : out std_logic
317
    );
318
  end component fifo_primitive;
319
 
320
  component first_stage is
321
    generic(
322
      width : integer := 16 -- must be the same as width of the standard stage
323
    );
324
    port(
325
      core_clk : in  std_logic;
326
      my       : in  std_logic_vector((width) downto 0);
327
      y        : in  std_logic_vector((width) downto 0);
328
      m        : in  std_logic_vector((width) downto 0);
329
      xin      : in  std_logic;
330
      xout     : out std_logic;
331
      qout     : out std_logic;
332
      a_msb    : in  std_logic;
333
      cout     : out std_logic;
334
      start    : in  std_logic;
335
      reset    : in  std_logic;
336
      done     : out std_logic;
337
      r        : out std_logic_vector((width-1) downto 0)
338
    );
339
  end component first_stage;
340
 
341
  component last_stage is
342
    generic(
343
      width : integer := 16 -- must be the same as width of the standard stage
344
    );
345
    port(
346
      core_clk : in  std_logic;
347
      my       : in  std_logic_vector((width-1) downto 0);
348
      y        : in  std_logic_vector((width-2) downto 0);
349
      m        : in  std_logic_vector((width-2) downto 0);
350
      xin      : in  std_logic;
351
      qin      : in  std_logic;
352
      cin      : in  std_logic;
353
      start    : in  std_logic;
354
      reset    : in  std_logic;
355
      r        : out std_logic_vector((width+1) downto 0)
356
    );
357
  end component last_stage;
358
 
359
  component modulus_ram is
360
    port(
361
      clk           : in std_logic;
362
      modulus_addr  : in std_logic_vector(5 downto 0);
363
      write_modulus : in std_logic;
364
      modulus_in    : in std_logic_vector(31 downto 0);
365
      modulus_out   : out std_logic_vector(1535 downto 0)
366
    );
367
  end component modulus_ram;
368
 
369
  component mont_ctrl is
370
    port (
371
      clk   : in std_logic;
372
      reset : in std_logic;
373
        -- bus side
374
      start           : in std_logic;
375
      x_sel_single    : in std_logic_vector(1 downto 0);
376
      y_sel_single    : in std_logic_vector(1 downto 0);
377
      run_auto        : in std_logic;
378
      op_buffer_empty : in std_logic;
379
      op_sel_buffer   : in std_logic_vector(31 downto 0);
380
      read_buffer     : out std_logic;
381
      buffer_noread   : in std_logic;
382
      done            : out std_logic;
383
      calc_time       : out std_logic;
384
        -- multiplier side
385
      op_sel           : out std_logic_vector(1 downto 0);
386
      load_x           : out std_logic;
387
      load_result      : out std_logic;
388
      start_multiplier : out std_logic;
389
      multiplier_ready : in std_logic
390
    );
391
  end component mont_ctrl;
392
 
393
  component mont_mult_sys_pipeline is
394
    generic (
395
      n          : integer := 1536;
396
      nr_stages  : integer := 96; --(divides n, bits_low & (n-bits_low))
397
      stages_low : integer := 32
398
    );
399
    port (
400
      core_clk : in std_logic;
401
      xy       : in std_logic_vector((n-1) downto 0);
402
      m        : in std_logic_vector((n-1) downto 0);
403
      r        : out std_logic_vector((n-1) downto 0);
404
      start    : in std_logic;
405
      reset    : in std_logic;
406
      p_sel    : in std_logic_vector(1 downto 0);
407
      load_x   : in std_logic;
408
      ready    : out std_logic
409
    );
410
  end component mont_mult_sys_pipeline;
411
 
412
  component multiplier_core is
413
    port(
414
      clk   : in  std_logic;
415
      reset : in  std_logic;
416
        -- operand memory interface (plb shared memory)
417
      write_enable : in  std_logic;
418
      data_in      : in  std_logic_vector (31 downto 0);
419
      rw_address   : in  std_logic_vector (8 downto 0);
420
      data_out     : out std_logic_vector (31 downto 0);
421
      collision    : out std_logic;
422
        -- op_sel fifo interface
423
      fifo_din    : in  std_logic_vector (31 downto 0);
424
      fifo_push   : in  std_logic;
425
      fifo_full   : out std_logic;
426
      fifo_nopush : out std_logic;
427
        -- ctrl signals
428
      start          : in  std_logic;
429
      run_auto       : in  std_logic;
430
      ready          : out std_logic;
431
      x_sel_single   : in  std_logic_vector (1 downto 0);
432
      y_sel_single   : in  std_logic_vector (1 downto 0);
433
      dest_op_single : in  std_logic_vector (1 downto 0);
434
      p_sel          : in  std_logic_vector (1 downto 0);
435
      calc_time      : out std_logic
436
    );
437
  end component multiplier_core;
438
 
439
  component operand_dp is
440
    port (
441
      clka  : in std_logic;
442
      wea   : in std_logic_vector(0 downto 0);
443
      addra : in std_logic_vector(5 downto 0);
444
      dina  : in std_logic_vector(31 downto 0);
445
      douta : out std_logic_vector(511 downto 0);
446
      clkb  : in std_logic;
447
      web   : in std_logic_vector(0 downto 0);
448
      addrb : in std_logic_vector(5 downto 0);
449
      dinb  : in std_logic_vector(511 downto 0);
450
      doutb : out std_logic_vector(31 downto 0)
451
    );
452
  end component operand_dp;
453
 
454
  component operand_mem is
455
    generic(n : integer := 1536
456
    );
457
    port(
458
        -- data interface (plb side)
459
      data_in    : in  std_logic_vector(31 downto 0);
460
      data_out   : out  std_logic_vector(31 downto 0);
461
      rw_address : in  std_logic_vector(8 downto 0);
462
        -- address structure:
463
        -- bit:  8   -> '1': modulus
464
        --              '0': operands
465
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
466
        --              don't care in case of modulus
467
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
468
 
469
        -- operand interface (multiplier side)
470
      op_sel    : in  std_logic_vector(1 downto 0);
471
      xy_out    : out  std_logic_vector(1535 downto 0);
472
      m         : out  std_logic_vector(1535 downto 0);
473
      result_in : in std_logic_vector(1535 downto 0);
474
        -- control signals
475
      load_op        : in std_logic;
476
      load_m         : in std_logic;
477
      load_result    : in std_logic;
478
      result_dest_op : in std_logic_vector(1 downto 0);
479
      collision      : out std_logic;
480
        -- system clock
481
      clk : in  std_logic
482
    );
483
  end component operand_mem;
484
 
485
  component operand_ram is
486
    port( -- write_operand_ack voorzien?
487
      -- global ports
488
      clk       : in std_logic;
489
      collision : out std_logic;
490
      -- bus side connections (32-bit serial)
491
      operand_addr   : in std_logic_vector(5 downto 0);
492
      operand_in     : in std_logic_vector(31 downto 0);
493
      operand_in_sel : in std_logic_vector(1 downto 0);
494
      result_out     : out std_logic_vector(31 downto 0);
495
      write_operand  : in std_logic;
496
      -- multiplier side connections (1536 bit parallel)
497
      result_dest_op  : in std_logic_vector(1 downto 0);
498
      operand_out     : out std_logic_vector(1535 downto 0);
499
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
500
      write_result    : in std_logic;
501
      result_in       : in std_logic_vector(1535 downto 0)
502
    );
503
  end component operand_ram;
504
 
505
  component operands_sp is
506
    port (
507
      clka  : in std_logic;
508
      wea   : in std_logic_vector(0 downto 0);
509
      addra : in std_logic_vector(4 downto 0);
510
      dina  : in std_logic_vector(31 downto 0);
511
      douta : out std_logic_vector(511 downto 0)
512
    );
513
  end component operands_sp;
514
 
515
  component stepping_logic is
516
    generic(
517
      n : integer := 1536; -- max nr of steps required to complete a multiplication
518
      t : integer := 192 -- total nr of steps in the pipeline
519
    );
520
    port(
521
      core_clk          : in  std_logic;
522
      start             : in  std_logic;
523
      reset             : in  std_logic;
524
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
525
      n_sel             : in integer range 0 to n; -- nr of steps required for a complete multiplication
526
      start_first_stage : out std_logic;
527
      stepping_done     : out std_logic
528
    );
529
  end component stepping_logic;
530
 
531
  component systolic_pipeline is
532
    generic(
533
      n  : integer := 1536; -- width of the operands (# bits)
534
      t  : integer := 192;  -- number of stages (divider of n) >= 2
535
      tl : integer := 64    -- best take t = sqrt(n)
536
    );
537
    port(
538
      core_clk : in  std_logic;
539
      my       : in  std_logic_vector((n) downto 0);
540
      y        : in  std_logic_vector((n-1) downto 0);
541
      m        : in  std_logic_vector((n-1) downto 0);
542
      xi       : in  std_logic;
543
      start    : in  std_logic;
544
      reset    : in  std_logic;
545
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
546
      ready    : out std_logic;
547
      next_x   : out std_logic;
548
      r        : out std_logic_vector((n+1) downto 0)
549
    );
550
  end component systolic_pipeline;
551
 
552
  component x_shift_reg is
553
    generic(
554
      n  : integer := 1536;
555
      t  : integer := 48;
556
      tl : integer := 16
557
    );
558
    port(
559
      clk    : in  std_logic;
560
      reset  : in  std_logic;
561
      x_in   : in  std_logic_vector((n-1) downto 0);
562
      load_x : in  std_logic;
563
      next_x : in  std_logic;
564
      p_sel  : in  std_logic_vector(1 downto 0);
565
      x_i    : out std_logic
566
    );
567
  end component x_shift_reg;
568
 
569
end package mod_sim_exp_pkg;

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.