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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52
 
53 16 JonasDC
  --------------------------------------------------------------------
54
  -- d_flip_flop
55
  --------------------------------------------------------------------
56
  --    1-bit D flip-flop with asynchronous active high reset
57
  -- 
58 9 JonasDC
  component d_flip_flop is
59
    port(
60
      core_clk : in  std_logic; -- clock signal
61
      reset    : in  std_logic; -- active high reset
62
      din      : in  std_logic; -- data in
63
      dout     : out std_logic  -- data out
64 3 JonasDC
    );
65 9 JonasDC
  end component d_flip_flop;
66
 
67 16 JonasDC
  --------------------------------------------------------------------
68
  -- register_1b
69
  --------------------------------------------------------------------
70
  --    1-bit register with asynchronous reset and clock enable
71
  -- 
72 9 JonasDC
  component register_1b is
73
    port(
74
      core_clk : in  std_logic; -- clock input
75
      ce       : in  std_logic; -- clock enable (active high)
76
      reset    : in  std_logic; -- reset (active high)
77
      din      : in  std_logic; -- data in
78
      dout     : out std_logic  -- data out
79 3 JonasDC
    );
80 9 JonasDC
  end component register_1b;
81 3 JonasDC
 
82 16 JonasDC
  --------------------------------------------------------------------
83
  -- register_n
84
  --------------------------------------------------------------------
85
  --    n-bit register with asynchronous reset and clock enable
86
  -- 
87 9 JonasDC
  component register_n is
88
    generic(
89 16 JonasDC
      width : integer := 4
90 3 JonasDC
    );
91 9 JonasDC
    port(
92
      core_clk : in  std_logic; -- clock input
93
      ce       : in  std_logic; -- clock enable (active high)
94
      reset    : in  std_logic; -- reset (active high)
95 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
96
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
97 3 JonasDC
    );
98 9 JonasDC
  end component register_n;
99 3 JonasDC
 
100 16 JonasDC
  --------------------------------------------------------------------
101
  -- cell_1b_adder
102
  --------------------------------------------------------------------
103
  --    1-bit full adder cell using combinatorial logic
104
  --    
105 3 JonasDC
  component cell_1b_adder is
106
    port (
107 9 JonasDC
      -- input operands a, b
108
      a    : in  std_logic;
109
      b    : in  std_logic;
110
      -- carry in, out
111
      cin  : in  std_logic;
112
      cout : out  std_logic;
113
      -- result out
114
      r    : out  std_logic
115 3 JonasDC
    );
116
  end component cell_1b_adder;
117
 
118 16 JonasDC
  --------------------------------------------------------------------
119
  -- cell_1b_mux
120
  --------------------------------------------------------------------
121
  --    1-bit mux for a standard cell in the montgommery multiplier 
122
  --    systolic array
123
  -- 
124 3 JonasDC
  component cell_1b_mux is
125
    port (
126 9 JonasDC
      -- input bits
127
      my     : in  std_logic;
128 3 JonasDC
      y      : in  std_logic;
129
      m      : in  std_logic;
130 9 JonasDC
      -- selection bits
131 3 JonasDC
      x      : in  std_logic;
132
      q      : in  std_logic;
133 9 JonasDC
      -- mux out
134 3 JonasDC
      result : out std_logic
135
    );
136
  end component cell_1b_mux;
137
 
138 16 JonasDC
  --------------------------------------------------------------------
139
  -- cell_1b
140
  --------------------------------------------------------------------
141
  --    1-bit cell for the systolic array
142
  -- 
143 3 JonasDC
  component cell_1b is
144
    port (
145 9 JonasDC
      -- operand input bits (m+y, y and m)
146 3 JonasDC
      my   : in  std_logic;
147
      y    : in  std_logic;
148
      m    : in  std_logic;
149 16 JonasDC
      -- operand x input bit and q
150 3 JonasDC
      x    : in  std_logic;
151
      q    : in  std_logic;
152 9 JonasDC
      -- previous result input bit
153 3 JonasDC
      a    : in  std_logic;
154 9 JonasDC
      -- carry's
155 3 JonasDC
      cin  : in  std_logic;
156
      cout : out std_logic;
157 9 JonasDC
      -- cell result out
158 3 JonasDC
      r    : out std_logic
159
    );
160
  end component cell_1b;
161
 
162 16 JonasDC
  --------------------------------------------------------------------
163
  -- adder_block
164
  --------------------------------------------------------------------
165
  --    (width)-bit full adder block using cell_1b_adders with buffered
166
  --    carry out
167
  -- 
168 9 JonasDC
  component adder_block is
169
    generic (
170
      width : integer := 32 --adder operand widths
171
    );
172
    port (
173
      -- clock input
174
      core_clk : in std_logic;
175
      -- adder input operands a, b (width)-bit
176
      a : in std_logic_vector((width-1) downto 0);
177
      b : in std_logic_vector((width-1) downto 0);
178
      -- carry in, out
179
      cin   : in std_logic;
180
      cout  : out std_logic;
181
      -- adder result out (width)-bit
182
      r : out std_logic_vector((width-1) downto 0)
183
    );
184
  end component adder_block;
185
 
186 16 JonasDC
  --------------------------------------------------------------------
187
  -- adder_n
188
  --------------------------------------------------------------------
189
  --    n-bit adder using adder blocks. works in stages, to prevent 
190
  --    large carry propagation. 
191
  --    Result avaiable after (width/block_width) clock cycles
192
  -- 
193 9 JonasDC
  component adder_n is
194
    generic (
195
      width       : integer := 1536; -- adder operands width
196
      block_width : integer := 8     -- adder blocks size
197
    );
198
    port (
199
      -- clock input
200
      core_clk : in std_logic;
201
      -- adder input operands (width)-bit
202
      a : in std_logic_vector((width-1) downto 0);
203
      b : in std_logic_vector((width-1) downto 0);
204
      -- carry in, out
205
      cin   : in std_logic;
206
      cout  : out std_logic;
207
      -- adder output result (width)-bit
208
      r : out std_logic_vector((width-1) downto 0)
209
    );
210
  end component adder_n;
211
 
212 17 JonasDC
  --------------------------------------------------------------------
213
  -- standard_cell_block
214
  --------------------------------------------------------------------
215
  --    a standard cell block of (width)-bit for the montgommery multiplier 
216
  --    systolic array
217
  -- 
218
  component standard_cell_block is
219
    generic (
220
      width : integer := 16
221
    );
222
    port (
223
      -- modulus and y operand input (width)-bit
224
      my   : in  std_logic_vector((width-1) downto 0);
225
      y    : in  std_logic_vector((width-1) downto 0);
226
      m    : in  std_logic_vector((width-1) downto 0);
227
      -- q and x operand input (serial input)
228
      x    : in  std_logic;
229
      q    : in  std_logic;
230
      -- previous result in (width)-bit
231
      a    : in  std_logic_vector((width-1) downto 0);
232
      -- carry in and out
233
      cin  : in std_logic;
234
      cout : out std_logic;
235
      -- result out (width)-bit
236
      r    : out  std_logic_vector((width-1) downto 0)
237
    );
238
  end component standard_cell_block;
239
 
240
  --------------------------------------------------------------------
241
  -- standard_stage
242
  --------------------------------------------------------------------
243
  --    standard stage for use in the montgommery multiplier pipeline
244
  --    the result is available after 1 clock cycle
245
  -- 
246
  component standard_stage is
247
    generic(
248
      width : integer := 32
249
    );
250
    port(
251
      -- clock input
252
      core_clk : in  std_logic;
253
      -- modulus and y operand input (width)-bit
254
      my       : in  std_logic_vector((width-1) downto 0);
255
      y        : in  std_logic_vector((width-1) downto 0);
256
      m        : in  std_logic_vector((width-1) downto 0);
257
      -- q and x operand input (serial input)
258
      xin      : in  std_logic;
259
      qin      : in  std_logic;
260
      -- q and x operand output (serial output)
261
      xout     : out std_logic;
262
      qout     : out std_logic;
263
      -- msb input (lsb from next stage, for shift right operation)
264
      a_msb    : in  std_logic;
265
      -- carry out(clocked) and in
266
      cin      : in  std_logic;
267
      cout     : out std_logic;
268
      -- control singals
269
      start    : in  std_logic;
270
      reset    : in  std_logic;
271
      done : out std_logic;
272
      -- result out
273
      r    : out std_logic_vector((width-1) downto 0)
274
    );
275
  end component standard_stage;
276
 
277 18 JonasDC
  --------------------------------------------------------------------
278
  -- first_stage
279
  --------------------------------------------------------------------
280
  --    first stage for use in the montgommery multiplier pipeline
281
  --    generates the q signal for all following stages
282
  --    the result is available after 1 clock cycle
283
  -- 
284
  component first_stage is
285
    generic(
286
      width : integer := 16 -- must be the same as width of the standard stage
287
    );
288
    port(
289
      -- clock input
290
      core_clk : in  std_logic;
291
      -- modulus and y operand input (width+1)-bit
292
      my       : in  std_logic_vector((width) downto 0);
293
      y        : in  std_logic_vector((width) downto 0);
294
      m        : in  std_logic_vector((width) downto 0);
295
      -- x operand input (serial input)
296
      xin      : in  std_logic;
297
      -- q and x operand output (serial output)
298
      xout     : out std_logic;
299
      qout     : out std_logic;
300
      -- msb input (lsb from next stage, for shift right operation)
301
      a_msb    : in  std_logic;
302
      -- carry out
303
      cout     : out std_logic;
304
      -- control signals
305
      start    : in  std_logic;
306
      reset    : in  std_logic;
307
      done     : out std_logic;
308
      -- result out
309
      r        : out std_logic_vector((width-1) downto 0)
310
    );
311
  end component first_stage;
312
 
313
  --------------------------------------------------------------------
314
  -- last_stage
315
  --------------------------------------------------------------------
316
  --    last stage for use in the montgommery multiplier pipeline
317
  --    the result is available after 1 clock cycle
318
  -- 
319
  component last_stage is
320
    generic(
321
      width : integer := 16 -- must be the same as width of the standard stage
322
    );
323
    port(
324
      -- clock input
325
      core_clk : in  std_logic;
326
      -- modulus and y operand input (width(-1))-bit
327
      my       : in  std_logic_vector((width-1) downto 0);
328
      y        : in  std_logic_vector((width-2) downto 0);
329
      m        : in  std_logic_vector((width-2) downto 0);
330
      -- q and x operand input (serial input)
331
      xin      : in  std_logic;
332
      qin      : in  std_logic;
333
      -- carry in
334
      cin      : in  std_logic;
335
      -- control signals
336
      start    : in  std_logic;
337
      reset    : in  std_logic;
338
      -- result out
339
      r        : out std_logic_vector((width+1) downto 0)
340
    );
341
  end component last_stage;
342
 
343 19 JonasDC
  --------------------------------------------------------------------
344
  -- counter_sync
345
  --------------------------------------------------------------------
346
  --    counter with synchronous count enable. It generates an
347
  --    overflow when max_value is reached
348
  -- 
349
  component counter_sync is
350
    generic(
351
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
352
    );
353
    port(
354
      reset_value : in integer;   -- value the counter counts to
355
      core_clk    : in std_logic; -- clock input
356
      ce          : in std_logic; -- count enable
357
      reset       : in std_logic; -- reset input
358
      overflow    : out std_logic -- gets high when counter reaches reset_value
359
    );
360
  end component counter_sync;
361 18 JonasDC
 
362 19 JonasDC
  --------------------------------------------------------------------
363
  -- stepping_logic
364
  --------------------------------------------------------------------
365
  --    stepping logic for the pipeline, generates the start pulses for the
366
  --    first stage and keeps track of when the last stages are done
367
  -- 
368
  component stepping_logic is
369
    generic(
370
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
371
      t : integer := 192    -- total nr of steps in the pipeline
372
    );
373
    port(
374
      core_clk          : in  std_logic;  -- clock input
375
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
376
      reset             : in  std_logic;  -- reset signal
377
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
378
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
379
      start_first_stage : out std_logic;  -- start pulse output for first stage
380
      stepping_done     : out std_logic   -- done signal
381
    );
382
  end component stepping_logic;
383
 
384 20 JonasDC
  --------------------------------------------------------------------
385
  -- x_shift_reg
386
  --------------------------------------------------------------------
387
  --    shift register for the x operand of the multiplier
388
  --    outputs the lsb of the register or bit at offset according to the
389
  --    selected pipeline part 
390
  -- 
391
  component x_shift_reg is
392
    generic(
393
      n  : integer := 1536; -- width of the operands (# bits)
394
      t  : integer := 48;   -- total number of stages
395
      tl : integer := 16    -- lower number of stages
396
    );
397
    port(
398
      -- clock input
399
      clk    : in  std_logic;
400
      -- x operand in (n-bit)
401
      x_in   : in  std_logic_vector((n-1) downto 0);
402
      -- control signals
403
      reset  : in  std_logic; -- reset, clears register
404
      load_x : in  std_logic; -- load operand into shift register   
405
      next_x : in  std_logic; -- next bit of x
406
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
407
      -- x operand bit out (serial)
408 21 JonasDC
      xi     : out std_logic
409 20 JonasDC
    );
410
  end component x_shift_reg;
411
 
412 22 JonasDC
  --------------------------------------------------------------------
413
  -- systolic_pipeline
414
  --------------------------------------------------------------------
415
  --    systolic pipeline implementation of the montgommery multiplier
416
  --    devides the pipeline into 2 parts, so 3 operand widths are supported
417
  -- 
418
  --    p_sel: 
419
  --      01 = lower part
420
  --      10 = upper part
421
  --      11 = full range
422
  component systolic_pipeline is
423
    generic(
424
      n  : integer := 1536; -- width of the operands (# bits)
425
      t  : integer := 192;  -- total number of stages (divider of n) >= 2
426
      tl : integer := 64    -- lower number of stages (best take t = sqrt(n))
427
    );
428
    port(
429
      -- clock input
430
      core_clk : in  std_logic;
431
      -- modulus and y opperand input (n)-bit
432
      my       : in  std_logic_vector((n) downto 0); -- m+y
433
      y        : in  std_logic_vector((n-1) downto 0);
434
      m        : in  std_logic_vector((n-1) downto 0);
435
      -- x operand input (serial)
436
      xi       : in  std_logic;
437
      -- control signals
438
      start    : in  std_logic; -- start multiplier
439
      reset    : in  std_logic;
440
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
441
      ready    : out std_logic; -- multiplication ready
442
      next_x   : out std_logic; -- next x operand bit
443
      -- result out
444
      r        : out std_logic_vector((n+1) downto 0)
445
    );
446
  end component systolic_pipeline;
447
 
448 23 JonasDC
  --------------------------------------------------------------------
449
  -- mont_mult_sys_pipeline
450
  --------------------------------------------------------------------
451
  -- Structural description of the montgommery multiply pipeline
452
  -- contains the x operand shift register, my adder, the pipeline and 
453
  -- reduction adder. To do a multiplication, the following actions must take place:
454
  -- 
455
  --    * load in the x operand in the shift register using the xy bus and load_x
456
  --    * place the y operand on the xy bus for the rest of the operation
457
  --    * generate a start pulse of 1 clk cycle long on start
458
  --    * wait for ready signal
459
  --    * result is avaiable on the r bus
460
  -- 
461
  component mont_mult_sys_pipeline is
462
    generic (
463
      n          : integer := 1536; -- width of the operands
464
      nr_stages  : integer := 96; -- total number of stages
465
      stages_low : integer := 32  -- lower number of stages
466
    );
467
    port (
468
      -- clock input
469
      core_clk : in std_logic;
470
      -- operand inputs
471
      xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
472
      m        : in std_logic_vector((n-1) downto 0); -- modulus
473
      -- result output
474
      r        : out std_logic_vector((n-1) downto 0);  -- result
475
      -- control signals
476
      start    : in std_logic;
477
      reset    : in std_logic;
478
      p_sel    : in std_logic_vector(1 downto 0);
479
      load_x   : in std_logic;
480
      ready    : out std_logic
481
    );
482
  end component mont_mult_sys_pipeline;
483
 
484 24 JonasDC
  --------------------------------------------------------------------
485
  -- mod_sim_exp_core
486
  --------------------------------------------------------------------
487
  --    toplevel of the modular simultaneous exponentiation core
488
  --    contains an operand and modulus ram, multiplier, an exponent fifo
489
  --    and control logic
490
  -- 
491
  component mod_sim_exp_core is
492
    port(
493
      clk   : in  std_logic;
494
      reset : in  std_logic;
495
        -- operand memory interface (plb shared memory)
496
      write_enable : in  std_logic; -- write data to operand ram
497
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
498
      rw_address   : in  std_logic_vector (8 downto 0);   -- operand ram address bus
499
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
500
      collision    : out std_logic; -- write collision
501
        -- op_sel fifo interface
502
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
503
      fifo_push   : in  std_logic;  -- push data in exponent fifo
504
      fifo_full   : out std_logic;  -- high if fifo is full
505
      fifo_nopush : out std_logic;  -- high if error during push
506
        -- control signals
507
      start          : in  std_logic; -- start multiplication/exponentiation
508
      run_auto       : in  std_logic; -- single multiplication if low, exponentiation if high
509
      ready          : out std_logic; -- calculations done
510
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
511
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
512
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
513
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
514
      calc_time      : out std_logic
515
    );
516
  end component mod_sim_exp_core;
517
 
518 9 JonasDC
  component autorun_cntrl is
519
    port (
520
      clk              : in  std_logic;
521
      reset            : in  std_logic;
522
      start            : in  std_logic;
523
      done             : out  std_logic;
524
      op_sel           : out  std_logic_vector (1 downto 0);
525
      start_multiplier : out  std_logic;
526
      multiplier_done  : in  std_logic;
527
      read_buffer      : out  std_logic;
528
      buffer_din       : in  std_logic_vector (31 downto 0);
529
      buffer_empty     : in  std_logic
530
    );
531
  end component autorun_cntrl;
532
 
533 3 JonasDC
  component fifo_primitive is
534
    port (
535
      clk    : in  std_logic;
536
      din    : in  std_logic_vector (31 downto 0);
537
      dout   : out  std_logic_vector (31 downto 0);
538
      empty  : out  std_logic;
539
      full   : out  std_logic;
540
      push   : in  std_logic;
541
      pop    : in  std_logic;
542
      reset  : in std_logic;
543
      nopop  : out std_logic;
544
      nopush : out std_logic
545
    );
546
  end component fifo_primitive;
547
 
548
  component modulus_ram is
549
    port(
550
      clk           : in std_logic;
551
      modulus_addr  : in std_logic_vector(5 downto 0);
552
      write_modulus : in std_logic;
553
      modulus_in    : in std_logic_vector(31 downto 0);
554
      modulus_out   : out std_logic_vector(1535 downto 0)
555
    );
556
  end component modulus_ram;
557
 
558
  component mont_ctrl is
559
    port (
560
      clk   : in std_logic;
561
      reset : in std_logic;
562
        -- bus side
563
      start           : in std_logic;
564
      x_sel_single    : in std_logic_vector(1 downto 0);
565
      y_sel_single    : in std_logic_vector(1 downto 0);
566
      run_auto        : in std_logic;
567
      op_buffer_empty : in std_logic;
568
      op_sel_buffer   : in std_logic_vector(31 downto 0);
569
      read_buffer     : out std_logic;
570
      buffer_noread   : in std_logic;
571
      done            : out std_logic;
572
      calc_time       : out std_logic;
573
        -- multiplier side
574
      op_sel           : out std_logic_vector(1 downto 0);
575
      load_x           : out std_logic;
576
      load_result      : out std_logic;
577
      start_multiplier : out std_logic;
578
      multiplier_ready : in std_logic
579
    );
580
  end component mont_ctrl;
581
 
582
  component operand_dp is
583
    port (
584
      clka  : in std_logic;
585
      wea   : in std_logic_vector(0 downto 0);
586
      addra : in std_logic_vector(5 downto 0);
587
      dina  : in std_logic_vector(31 downto 0);
588
      douta : out std_logic_vector(511 downto 0);
589
      clkb  : in std_logic;
590
      web   : in std_logic_vector(0 downto 0);
591
      addrb : in std_logic_vector(5 downto 0);
592
      dinb  : in std_logic_vector(511 downto 0);
593
      doutb : out std_logic_vector(31 downto 0)
594
    );
595
  end component operand_dp;
596
 
597
  component operand_mem is
598
    generic(n : integer := 1536
599
    );
600
    port(
601
        -- data interface (plb side)
602
      data_in    : in  std_logic_vector(31 downto 0);
603
      data_out   : out  std_logic_vector(31 downto 0);
604
      rw_address : in  std_logic_vector(8 downto 0);
605
        -- address structure:
606
        -- bit:  8   -> '1': modulus
607
        --              '0': operands
608
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
609
        --              don't care in case of modulus
610
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
611
 
612
        -- operand interface (multiplier side)
613
      op_sel    : in  std_logic_vector(1 downto 0);
614
      xy_out    : out  std_logic_vector(1535 downto 0);
615
      m         : out  std_logic_vector(1535 downto 0);
616
      result_in : in std_logic_vector(1535 downto 0);
617
        -- control signals
618
      load_op        : in std_logic;
619
      load_m         : in std_logic;
620
      load_result    : in std_logic;
621
      result_dest_op : in std_logic_vector(1 downto 0);
622
      collision      : out std_logic;
623
        -- system clock
624
      clk : in  std_logic
625
    );
626
  end component operand_mem;
627
 
628
  component operand_ram is
629
    port( -- write_operand_ack voorzien?
630
      -- global ports
631
      clk       : in std_logic;
632
      collision : out std_logic;
633
      -- bus side connections (32-bit serial)
634
      operand_addr   : in std_logic_vector(5 downto 0);
635
      operand_in     : in std_logic_vector(31 downto 0);
636
      operand_in_sel : in std_logic_vector(1 downto 0);
637
      result_out     : out std_logic_vector(31 downto 0);
638
      write_operand  : in std_logic;
639
      -- multiplier side connections (1536 bit parallel)
640
      result_dest_op  : in std_logic_vector(1 downto 0);
641
      operand_out     : out std_logic_vector(1535 downto 0);
642
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
643
      write_result    : in std_logic;
644
      result_in       : in std_logic_vector(1535 downto 0)
645
    );
646
  end component operand_ram;
647
 
648
  component operands_sp is
649
    port (
650
      clka  : in std_logic;
651
      wea   : in std_logic_vector(0 downto 0);
652
      addra : in std_logic_vector(4 downto 0);
653
      dina  : in std_logic_vector(31 downto 0);
654
      douta : out std_logic_vector(511 downto 0)
655
    );
656
  end component operands_sp;
657
 
658 25 JonasDC
 
659
  component sys_stage is
660
    generic(
661
      width : integer := 32 -- width of the stage
662
    );
663
    port(
664
      -- clock input
665
      core_clk : in  std_logic;
666
      -- modulus and y operand input (width)-bit
667
      y        : in  std_logic_vector((width-1) downto 0);
668
      m        : in  std_logic_vector((width) downto 0);
669
      my_cin   : in  std_logic;
670
      my_cout  : out std_logic;
671
      -- q and x operand input (serial input)
672
      xin      : in  std_logic;
673
      qin      : in  std_logic;
674
      -- q and x operand output (serial output)
675
      xout     : out std_logic;
676
      qout     : out std_logic;
677
      -- msb input (lsb from next stage, for shift right operation)
678
      a_msb    : in  std_logic;
679
      a_0      : out std_logic;
680
      -- carry out(clocked) and in
681
      cin      : in  std_logic;
682
      cout     : out std_logic;
683
      -- reduction adder carry's
684
      red_cin  : in std_logic;
685
      red_cout : out std_logic;
686
      -- control singals
687
      start    : in  std_logic;
688
      reset    : in  std_logic;
689
      done     : out std_logic;
690
      -- result out
691
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
692
      r        : out std_logic_vector((width-1) downto 0)
693
    );
694
  end component sys_stage;
695 30 JonasDC
 
696
  --------------------------------------------------------------------
697
  -- sys_last_cell_logic
698
  --------------------------------------------------------------------   
699
  --    logic needed as the last piece in the systolic array pipeline
700
  --    calculates the last 2 bits of the cell_result and finishes the reduction
701
  --    also generates the result selection signal
702
  -- 
703
  component sys_last_cell_logic is
704
    port  (
705
      core_clk : in std_logic;    -- clock input
706
      reset    : in std_logic;
707
      a_0      : out std_logic;   -- a_msb for last stage
708
      cin      : in std_logic;    -- cout from last stage
709
      red_cin  : in std_logic;    -- red_cout from last stage
710
      r_sel    : out std_logic;   -- result selection bit
711
      start    : in std_logic     -- done signal from last stage
712
    );
713
  end component sys_last_cell_logic;
714 25 JonasDC
 
715
  --------------------------------------------------------------------
716 31 JonasDC
  -- sys_first_cell_logic
717
  --------------------------------------------------------------------     
718
  --    logic needed as the first piece in the systolic array pipeline
719
  --    calculates the first my_cout and generates q signal
720
  -- 
721
  component sys_first_cell_logic is
722
    port  (
723
      m0       : in std_logic;    -- lsb from m operand
724
      y0       : in std_logic;    -- lsb from y operand
725
      my_cout  : out std_logic;   -- my_cin for first stage
726
      xi       : in std_logic;    -- xi operand input
727
      xout     : out std_logic;   -- xin for first stage
728
      qout     : out std_logic;   -- qin for first stage
729
      cout     : out std_logic;   -- cin for first stage
730
      a_0      : in std_logic;    -- a_0 from first stage
731
      red_cout : out std_logic    -- red_cin for first stage
732
    );
733
  end component sys_first_cell_logic;
734
 
735
  --------------------------------------------------------------------
736 25 JonasDC
  -- sys_pipeline
737
  -------------------------------------------------------------------- 
738
  --    the pipelined systolic array for a montgommery multiplier
739
  --    contains a structural description of the pipeline using the systolic stages
740
  -- 
741
  component sys_pipeline is
742
    generic(
743
      n  : integer := 1536; -- width of the operands (# bits)
744
      t  : integer := 192;  -- total number of stages (divider of n) >= 2
745
      tl : integer := 64    -- lower number of stages (best take t = sqrt(n))
746
    );
747
    port(
748
      -- clock input
749
      core_clk : in  std_logic;
750
      -- modulus and y opperand input (n)-bit
751
      y        : in  std_logic_vector((n-1) downto 0);
752
      m        : in  std_logic_vector((n-1) downto 0);
753
      -- x operand input (serial)
754
      xi       : in  std_logic;
755
      next_x   : out std_logic; -- next x operand bit
756
      -- control signals
757
      start    : in  std_logic; -- start multiplier
758
      reset    : in  std_logic;
759
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
760
      -- result out
761
      r        : out std_logic_vector((n-1) downto 0)
762
    );
763
  end component sys_pipeline;
764
 
765
  component mont_multiplier is
766
  generic (
767
    n          : integer := 1536; -- width of the operands
768
    nr_stages  : integer := 96; -- total number of stages
769
    stages_low : integer := 32  -- lower number of stages
770
  );
771
  port (
772
    -- clock input
773
    core_clk : in std_logic;
774
    -- operand inputs
775
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
776
    m        : in std_logic_vector((n-1) downto 0); -- modulus
777
    -- result output
778
    r        : out std_logic_vector((n-1) downto 0);  -- result
779
    -- control signals
780
    start    : in std_logic;
781
    reset    : in std_logic;
782
    p_sel    : in std_logic_vector(1 downto 0);
783
    load_x   : in std_logic;
784
    ready    : out std_logic
785
  );
786
  end component mont_multiplier;
787
 
788 3 JonasDC
end package mod_sim_exp_pkg;

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