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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52 37 JonasDC
  --------------------------------------------------------------------
53
  ------------------------- CORE PARAMETERS --------------------------
54
  --------------------------------------------------------------------
55
  -- These 4 parameters affect core workings
56
  constant nr_bits_total    : integer := 1536;
57
  constant nr_stages_total  : integer := 96;
58
  constant nr_stages_low    : integer := 32;
59
  constant split_pipeline   : boolean := true;
60 3 JonasDC
 
61 37 JonasDC
  -- extra calculated parameters
62
  constant nr_bits_low      : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
63
  constant nr_bits_high     : integer := nr_bits_total-nr_bits_low;
64
  constant nr_stages_high   : integer := nr_stages_total-nr_stages_low;
65
 
66
 
67 16 JonasDC
  --------------------------------------------------------------------
68 37 JonasDC
  ---------------------- COMPONENT DECLARATIONS ----------------------
69
  --------------------------------------------------------------------
70
 
71
  --------------------------------------------------------------------
72 16 JonasDC
  -- d_flip_flop
73
  --------------------------------------------------------------------
74
  --    1-bit D flip-flop with asynchronous active high reset
75
  -- 
76 9 JonasDC
  component d_flip_flop is
77
    port(
78
      core_clk : in  std_logic; -- clock signal
79
      reset    : in  std_logic; -- active high reset
80
      din      : in  std_logic; -- data in
81
      dout     : out std_logic  -- data out
82 3 JonasDC
    );
83 9 JonasDC
  end component d_flip_flop;
84
 
85 16 JonasDC
  --------------------------------------------------------------------
86
  -- register_1b
87
  --------------------------------------------------------------------
88
  --    1-bit register with asynchronous reset and clock enable
89
  -- 
90 9 JonasDC
  component register_1b is
91
    port(
92
      core_clk : in  std_logic; -- clock input
93
      ce       : in  std_logic; -- clock enable (active high)
94
      reset    : in  std_logic; -- reset (active high)
95
      din      : in  std_logic; -- data in
96
      dout     : out std_logic  -- data out
97 3 JonasDC
    );
98 9 JonasDC
  end component register_1b;
99 3 JonasDC
 
100 16 JonasDC
  --------------------------------------------------------------------
101
  -- register_n
102
  --------------------------------------------------------------------
103
  --    n-bit register with asynchronous reset and clock enable
104
  -- 
105 9 JonasDC
  component register_n is
106
    generic(
107 16 JonasDC
      width : integer := 4
108 3 JonasDC
    );
109 9 JonasDC
    port(
110
      core_clk : in  std_logic; -- clock input
111
      ce       : in  std_logic; -- clock enable (active high)
112
      reset    : in  std_logic; -- reset (active high)
113 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
114
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
115 3 JonasDC
    );
116 9 JonasDC
  end component register_n;
117 3 JonasDC
 
118 16 JonasDC
  --------------------------------------------------------------------
119
  -- cell_1b_adder
120
  --------------------------------------------------------------------
121
  --    1-bit full adder cell using combinatorial logic
122
  --    
123 3 JonasDC
  component cell_1b_adder is
124
    port (
125 9 JonasDC
      -- input operands a, b
126
      a    : in  std_logic;
127
      b    : in  std_logic;
128
      -- carry in, out
129
      cin  : in  std_logic;
130
      cout : out  std_logic;
131
      -- result out
132
      r    : out  std_logic
133 3 JonasDC
    );
134
  end component cell_1b_adder;
135
 
136 16 JonasDC
  --------------------------------------------------------------------
137
  -- cell_1b_mux
138
  --------------------------------------------------------------------
139
  --    1-bit mux for a standard cell in the montgommery multiplier 
140
  --    systolic array
141
  -- 
142 3 JonasDC
  component cell_1b_mux is
143
    port (
144 9 JonasDC
      -- input bits
145
      my     : in  std_logic;
146 3 JonasDC
      y      : in  std_logic;
147
      m      : in  std_logic;
148 9 JonasDC
      -- selection bits
149 3 JonasDC
      x      : in  std_logic;
150
      q      : in  std_logic;
151 9 JonasDC
      -- mux out
152 3 JonasDC
      result : out std_logic
153
    );
154
  end component cell_1b_mux;
155
 
156 16 JonasDC
  --------------------------------------------------------------------
157
  -- cell_1b
158
  --------------------------------------------------------------------
159
  --    1-bit cell for the systolic array
160
  -- 
161 3 JonasDC
  component cell_1b is
162
    port (
163 9 JonasDC
      -- operand input bits (m+y, y and m)
164 3 JonasDC
      my   : in  std_logic;
165
      y    : in  std_logic;
166
      m    : in  std_logic;
167 16 JonasDC
      -- operand x input bit and q
168 3 JonasDC
      x    : in  std_logic;
169
      q    : in  std_logic;
170 9 JonasDC
      -- previous result input bit
171 3 JonasDC
      a    : in  std_logic;
172 9 JonasDC
      -- carry's
173 3 JonasDC
      cin  : in  std_logic;
174
      cout : out std_logic;
175 9 JonasDC
      -- cell result out
176 3 JonasDC
      r    : out std_logic
177
    );
178
  end component cell_1b;
179
 
180 16 JonasDC
  --------------------------------------------------------------------
181
  -- adder_block
182
  --------------------------------------------------------------------
183
  --    (width)-bit full adder block using cell_1b_adders with buffered
184
  --    carry out
185
  -- 
186 9 JonasDC
  component adder_block is
187
    generic (
188
      width : integer := 32 --adder operand widths
189
    );
190
    port (
191
      -- clock input
192
      core_clk : in std_logic;
193
      -- adder input operands a, b (width)-bit
194
      a : in std_logic_vector((width-1) downto 0);
195
      b : in std_logic_vector((width-1) downto 0);
196
      -- carry in, out
197
      cin   : in std_logic;
198
      cout  : out std_logic;
199
      -- adder result out (width)-bit
200
      r : out std_logic_vector((width-1) downto 0)
201
    );
202
  end component adder_block;
203
 
204 16 JonasDC
  --------------------------------------------------------------------
205
  -- adder_n
206
  --------------------------------------------------------------------
207
  --    n-bit adder using adder blocks. works in stages, to prevent 
208
  --    large carry propagation. 
209
  --    Result avaiable after (width/block_width) clock cycles
210
  -- 
211 9 JonasDC
  component adder_n is
212
    generic (
213
      width       : integer := 1536; -- adder operands width
214
      block_width : integer := 8     -- adder blocks size
215
    );
216
    port (
217
      -- clock input
218
      core_clk : in std_logic;
219
      -- adder input operands (width)-bit
220
      a : in std_logic_vector((width-1) downto 0);
221
      b : in std_logic_vector((width-1) downto 0);
222
      -- carry in, out
223
      cin   : in std_logic;
224
      cout  : out std_logic;
225
      -- adder output result (width)-bit
226
      r : out std_logic_vector((width-1) downto 0)
227
    );
228
  end component adder_n;
229
 
230 17 JonasDC
  --------------------------------------------------------------------
231
  -- standard_cell_block
232
  --------------------------------------------------------------------
233
  --    a standard cell block of (width)-bit for the montgommery multiplier 
234
  --    systolic array
235
  -- 
236
  component standard_cell_block is
237
    generic (
238
      width : integer := 16
239
    );
240
    port (
241
      -- modulus and y operand input (width)-bit
242
      my   : in  std_logic_vector((width-1) downto 0);
243
      y    : in  std_logic_vector((width-1) downto 0);
244
      m    : in  std_logic_vector((width-1) downto 0);
245
      -- q and x operand input (serial input)
246
      x    : in  std_logic;
247
      q    : in  std_logic;
248
      -- previous result in (width)-bit
249
      a    : in  std_logic_vector((width-1) downto 0);
250
      -- carry in and out
251
      cin  : in std_logic;
252
      cout : out std_logic;
253
      -- result out (width)-bit
254
      r    : out  std_logic_vector((width-1) downto 0)
255
    );
256
  end component standard_cell_block;
257
 
258
  --------------------------------------------------------------------
259
  -- standard_stage
260
  --------------------------------------------------------------------
261
  --    standard stage for use in the montgommery multiplier pipeline
262
  --    the result is available after 1 clock cycle
263
  -- 
264
  component standard_stage is
265
    generic(
266
      width : integer := 32
267
    );
268
    port(
269
      -- clock input
270
      core_clk : in  std_logic;
271
      -- modulus and y operand input (width)-bit
272
      my       : in  std_logic_vector((width-1) downto 0);
273
      y        : in  std_logic_vector((width-1) downto 0);
274
      m        : in  std_logic_vector((width-1) downto 0);
275
      -- q and x operand input (serial input)
276
      xin      : in  std_logic;
277
      qin      : in  std_logic;
278
      -- q and x operand output (serial output)
279
      xout     : out std_logic;
280
      qout     : out std_logic;
281
      -- msb input (lsb from next stage, for shift right operation)
282
      a_msb    : in  std_logic;
283
      -- carry out(clocked) and in
284
      cin      : in  std_logic;
285
      cout     : out std_logic;
286
      -- control singals
287
      start    : in  std_logic;
288
      reset    : in  std_logic;
289
      done : out std_logic;
290
      -- result out
291
      r    : out std_logic_vector((width-1) downto 0)
292
    );
293
  end component standard_stage;
294
 
295 18 JonasDC
  --------------------------------------------------------------------
296
  -- first_stage
297
  --------------------------------------------------------------------
298
  --    first stage for use in the montgommery multiplier pipeline
299
  --    generates the q signal for all following stages
300
  --    the result is available after 1 clock cycle
301
  -- 
302
  component first_stage is
303
    generic(
304
      width : integer := 16 -- must be the same as width of the standard stage
305
    );
306
    port(
307
      -- clock input
308
      core_clk : in  std_logic;
309
      -- modulus and y operand input (width+1)-bit
310
      my       : in  std_logic_vector((width) downto 0);
311
      y        : in  std_logic_vector((width) downto 0);
312
      m        : in  std_logic_vector((width) downto 0);
313
      -- x operand input (serial input)
314
      xin      : in  std_logic;
315
      -- q and x operand output (serial output)
316
      xout     : out std_logic;
317
      qout     : out std_logic;
318
      -- msb input (lsb from next stage, for shift right operation)
319
      a_msb    : in  std_logic;
320
      -- carry out
321
      cout     : out std_logic;
322
      -- control signals
323
      start    : in  std_logic;
324
      reset    : in  std_logic;
325
      done     : out std_logic;
326
      -- result out
327
      r        : out std_logic_vector((width-1) downto 0)
328
    );
329
  end component first_stage;
330
 
331
  --------------------------------------------------------------------
332
  -- last_stage
333
  --------------------------------------------------------------------
334
  --    last stage for use in the montgommery multiplier pipeline
335
  --    the result is available after 1 clock cycle
336
  -- 
337
  component last_stage is
338
    generic(
339
      width : integer := 16 -- must be the same as width of the standard stage
340
    );
341
    port(
342
      -- clock input
343
      core_clk : in  std_logic;
344
      -- modulus and y operand input (width(-1))-bit
345
      my       : in  std_logic_vector((width-1) downto 0);
346
      y        : in  std_logic_vector((width-2) downto 0);
347
      m        : in  std_logic_vector((width-2) downto 0);
348
      -- q and x operand input (serial input)
349
      xin      : in  std_logic;
350
      qin      : in  std_logic;
351
      -- carry in
352
      cin      : in  std_logic;
353
      -- control signals
354
      start    : in  std_logic;
355
      reset    : in  std_logic;
356
      -- result out
357
      r        : out std_logic_vector((width+1) downto 0)
358
    );
359
  end component last_stage;
360
 
361 19 JonasDC
  --------------------------------------------------------------------
362
  -- counter_sync
363
  --------------------------------------------------------------------
364
  --    counter with synchronous count enable. It generates an
365
  --    overflow when max_value is reached
366
  -- 
367
  component counter_sync is
368
    generic(
369
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
370
    );
371
    port(
372
      reset_value : in integer;   -- value the counter counts to
373
      core_clk    : in std_logic; -- clock input
374
      ce          : in std_logic; -- count enable
375
      reset       : in std_logic; -- reset input
376
      overflow    : out std_logic -- gets high when counter reaches reset_value
377
    );
378
  end component counter_sync;
379 18 JonasDC
 
380 19 JonasDC
  --------------------------------------------------------------------
381
  -- stepping_logic
382
  --------------------------------------------------------------------
383
  --    stepping logic for the pipeline, generates the start pulses for the
384
  --    first stage and keeps track of when the last stages are done
385
  -- 
386
  component stepping_logic is
387
    generic(
388
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
389
      t : integer := 192    -- total nr of steps in the pipeline
390
    );
391
    port(
392
      core_clk          : in  std_logic;  -- clock input
393
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
394
      reset             : in  std_logic;  -- reset signal
395
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
396
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
397
      start_first_stage : out std_logic;  -- start pulse output for first stage
398
      stepping_done     : out std_logic   -- done signal
399
    );
400
  end component stepping_logic;
401
 
402 20 JonasDC
  --------------------------------------------------------------------
403
  -- x_shift_reg
404
  --------------------------------------------------------------------
405
  --    shift register for the x operand of the multiplier
406
  --    outputs the lsb of the register or bit at offset according to the
407
  --    selected pipeline part 
408
  -- 
409
  component x_shift_reg is
410
    generic(
411
      n  : integer := 1536; -- width of the operands (# bits)
412
      t  : integer := 48;   -- total number of stages
413
      tl : integer := 16    -- lower number of stages
414
    );
415
    port(
416
      -- clock input
417
      clk    : in  std_logic;
418
      -- x operand in (n-bit)
419
      x_in   : in  std_logic_vector((n-1) downto 0);
420
      -- control signals
421
      reset  : in  std_logic; -- reset, clears register
422
      load_x : in  std_logic; -- load operand into shift register   
423
      next_x : in  std_logic; -- next bit of x
424
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
425
      -- x operand bit out (serial)
426 21 JonasDC
      xi     : out std_logic
427 20 JonasDC
    );
428
  end component x_shift_reg;
429
 
430 22 JonasDC
  --------------------------------------------------------------------
431
  -- systolic_pipeline
432
  --------------------------------------------------------------------
433
  --    systolic pipeline implementation of the montgommery multiplier
434
  --    devides the pipeline into 2 parts, so 3 operand widths are supported
435
  -- 
436
  --    p_sel: 
437
  --      01 = lower part
438
  --      10 = upper part
439
  --      11 = full range
440
  component systolic_pipeline is
441
    generic(
442
      n  : integer := 1536; -- width of the operands (# bits)
443
      t  : integer := 192;  -- total number of stages (divider of n) >= 2
444
      tl : integer := 64    -- lower number of stages (best take t = sqrt(n))
445
    );
446
    port(
447
      -- clock input
448
      core_clk : in  std_logic;
449
      -- modulus and y opperand input (n)-bit
450
      my       : in  std_logic_vector((n) downto 0); -- m+y
451
      y        : in  std_logic_vector((n-1) downto 0);
452
      m        : in  std_logic_vector((n-1) downto 0);
453
      -- x operand input (serial)
454
      xi       : in  std_logic;
455
      -- control signals
456
      start    : in  std_logic; -- start multiplier
457
      reset    : in  std_logic;
458
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
459
      ready    : out std_logic; -- multiplication ready
460
      next_x   : out std_logic; -- next x operand bit
461
      -- result out
462
      r        : out std_logic_vector((n+1) downto 0)
463
    );
464
  end component systolic_pipeline;
465
 
466 23 JonasDC
  --------------------------------------------------------------------
467
  -- mont_mult_sys_pipeline
468
  --------------------------------------------------------------------
469
  -- Structural description of the montgommery multiply pipeline
470
  -- contains the x operand shift register, my adder, the pipeline and 
471
  -- reduction adder. To do a multiplication, the following actions must take place:
472
  -- 
473
  --    * load in the x operand in the shift register using the xy bus and load_x
474
  --    * place the y operand on the xy bus for the rest of the operation
475
  --    * generate a start pulse of 1 clk cycle long on start
476
  --    * wait for ready signal
477
  --    * result is avaiable on the r bus
478
  -- 
479
  component mont_mult_sys_pipeline is
480
    generic (
481 37 JonasDC
      n  : integer := 1536; -- width of the operands
482
      t  : integer := 96;   -- total number of stages
483
      tl : integer := 32    -- lower number of stages
484 23 JonasDC
    );
485
    port (
486
      -- clock input
487
      core_clk : in std_logic;
488
      -- operand inputs
489
      xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
490
      m        : in std_logic_vector((n-1) downto 0); -- modulus
491
      -- result output
492
      r        : out std_logic_vector((n-1) downto 0);  -- result
493
      -- control signals
494
      start    : in std_logic;
495
      reset    : in std_logic;
496
      p_sel    : in std_logic_vector(1 downto 0);
497
      load_x   : in std_logic;
498
      ready    : out std_logic
499
    );
500
  end component mont_mult_sys_pipeline;
501
 
502 24 JonasDC
  --------------------------------------------------------------------
503
  -- mod_sim_exp_core
504
  --------------------------------------------------------------------
505
  --    toplevel of the modular simultaneous exponentiation core
506
  --    contains an operand and modulus ram, multiplier, an exponent fifo
507
  --    and control logic
508
  -- 
509
  component mod_sim_exp_core is
510
    port(
511
      clk   : in  std_logic;
512
      reset : in  std_logic;
513
        -- operand memory interface (plb shared memory)
514
      write_enable : in  std_logic; -- write data to operand ram
515
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
516
      rw_address   : in  std_logic_vector (8 downto 0);   -- operand ram address bus
517
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
518
      collision    : out std_logic; -- write collision
519
        -- op_sel fifo interface
520
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
521
      fifo_push   : in  std_logic;  -- push data in exponent fifo
522
      fifo_full   : out std_logic;  -- high if fifo is full
523
      fifo_nopush : out std_logic;  -- high if error during push
524
        -- control signals
525
      start          : in  std_logic; -- start multiplication/exponentiation
526
      run_auto       : in  std_logic; -- single multiplication if low, exponentiation if high
527
      ready          : out std_logic; -- calculations done
528
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
529
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
530
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
531
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
532
      calc_time      : out std_logic
533
    );
534
  end component mod_sim_exp_core;
535
 
536 9 JonasDC
  component autorun_cntrl is
537
    port (
538
      clk              : in  std_logic;
539
      reset            : in  std_logic;
540
      start            : in  std_logic;
541
      done             : out  std_logic;
542
      op_sel           : out  std_logic_vector (1 downto 0);
543
      start_multiplier : out  std_logic;
544
      multiplier_done  : in  std_logic;
545
      read_buffer      : out  std_logic;
546
      buffer_din       : in  std_logic_vector (31 downto 0);
547
      buffer_empty     : in  std_logic
548
    );
549
  end component autorun_cntrl;
550
 
551 3 JonasDC
  component fifo_primitive is
552
    port (
553
      clk    : in  std_logic;
554
      din    : in  std_logic_vector (31 downto 0);
555
      dout   : out  std_logic_vector (31 downto 0);
556
      empty  : out  std_logic;
557
      full   : out  std_logic;
558
      push   : in  std_logic;
559
      pop    : in  std_logic;
560
      reset  : in std_logic;
561
      nopop  : out std_logic;
562
      nopush : out std_logic
563
    );
564
  end component fifo_primitive;
565
 
566
  component modulus_ram is
567
    port(
568
      clk           : in std_logic;
569
      modulus_addr  : in std_logic_vector(5 downto 0);
570
      write_modulus : in std_logic;
571
      modulus_in    : in std_logic_vector(31 downto 0);
572
      modulus_out   : out std_logic_vector(1535 downto 0)
573
    );
574
  end component modulus_ram;
575
 
576
  component mont_ctrl is
577
    port (
578
      clk   : in std_logic;
579
      reset : in std_logic;
580
        -- bus side
581
      start           : in std_logic;
582
      x_sel_single    : in std_logic_vector(1 downto 0);
583
      y_sel_single    : in std_logic_vector(1 downto 0);
584
      run_auto        : in std_logic;
585
      op_buffer_empty : in std_logic;
586
      op_sel_buffer   : in std_logic_vector(31 downto 0);
587
      read_buffer     : out std_logic;
588
      buffer_noread   : in std_logic;
589
      done            : out std_logic;
590
      calc_time       : out std_logic;
591
        -- multiplier side
592
      op_sel           : out std_logic_vector(1 downto 0);
593
      load_x           : out std_logic;
594
      load_result      : out std_logic;
595
      start_multiplier : out std_logic;
596
      multiplier_ready : in std_logic
597
    );
598
  end component mont_ctrl;
599
 
600
  component operand_dp is
601
    port (
602
      clka  : in std_logic;
603
      wea   : in std_logic_vector(0 downto 0);
604
      addra : in std_logic_vector(5 downto 0);
605
      dina  : in std_logic_vector(31 downto 0);
606
      douta : out std_logic_vector(511 downto 0);
607
      clkb  : in std_logic;
608
      web   : in std_logic_vector(0 downto 0);
609
      addrb : in std_logic_vector(5 downto 0);
610
      dinb  : in std_logic_vector(511 downto 0);
611
      doutb : out std_logic_vector(31 downto 0)
612
    );
613
  end component operand_dp;
614
 
615
  component operand_mem is
616
    generic(n : integer := 1536
617
    );
618
    port(
619
        -- data interface (plb side)
620
      data_in    : in  std_logic_vector(31 downto 0);
621
      data_out   : out  std_logic_vector(31 downto 0);
622
      rw_address : in  std_logic_vector(8 downto 0);
623
        -- address structure:
624
        -- bit:  8   -> '1': modulus
625
        --              '0': operands
626
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
627
        --              don't care in case of modulus
628
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
629
 
630
        -- operand interface (multiplier side)
631
      op_sel    : in  std_logic_vector(1 downto 0);
632 34 JonasDC
      xy_out    : out  std_logic_vector((n-1) downto 0);
633
      m         : out  std_logic_vector((n-1) downto 0);
634
      result_in : in std_logic_vector((n-1) downto 0);
635 3 JonasDC
        -- control signals
636
      load_op        : in std_logic;
637
      load_m         : in std_logic;
638
      load_result    : in std_logic;
639
      result_dest_op : in std_logic_vector(1 downto 0);
640
      collision      : out std_logic;
641
        -- system clock
642
      clk : in  std_logic
643
    );
644
  end component operand_mem;
645
 
646
  component operand_ram is
647
    port( -- write_operand_ack voorzien?
648
      -- global ports
649
      clk       : in std_logic;
650
      collision : out std_logic;
651
      -- bus side connections (32-bit serial)
652
      operand_addr   : in std_logic_vector(5 downto 0);
653
      operand_in     : in std_logic_vector(31 downto 0);
654
      operand_in_sel : in std_logic_vector(1 downto 0);
655
      result_out     : out std_logic_vector(31 downto 0);
656
      write_operand  : in std_logic;
657
      -- multiplier side connections (1536 bit parallel)
658
      result_dest_op  : in std_logic_vector(1 downto 0);
659
      operand_out     : out std_logic_vector(1535 downto 0);
660
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
661
      write_result    : in std_logic;
662
      result_in       : in std_logic_vector(1535 downto 0)
663
    );
664
  end component operand_ram;
665
 
666
  component operands_sp is
667
    port (
668
      clka  : in std_logic;
669
      wea   : in std_logic_vector(0 downto 0);
670
      addra : in std_logic_vector(4 downto 0);
671
      dina  : in std_logic_vector(31 downto 0);
672
      douta : out std_logic_vector(511 downto 0)
673
    );
674
  end component operands_sp;
675
 
676 25 JonasDC
 
677
  component sys_stage is
678
    generic(
679
      width : integer := 32 -- width of the stage
680
    );
681
    port(
682
      -- clock input
683
      core_clk : in  std_logic;
684
      -- modulus and y operand input (width)-bit
685
      y        : in  std_logic_vector((width-1) downto 0);
686
      m        : in  std_logic_vector((width) downto 0);
687
      my_cin   : in  std_logic;
688
      my_cout  : out std_logic;
689
      -- q and x operand input (serial input)
690
      xin      : in  std_logic;
691
      qin      : in  std_logic;
692
      -- q and x operand output (serial output)
693
      xout     : out std_logic;
694
      qout     : out std_logic;
695
      -- msb input (lsb from next stage, for shift right operation)
696
      a_msb    : in  std_logic;
697
      a_0      : out std_logic;
698
      -- carry out(clocked) and in
699
      cin      : in  std_logic;
700
      cout     : out std_logic;
701
      -- reduction adder carry's
702
      red_cin  : in std_logic;
703
      red_cout : out std_logic;
704
      -- control singals
705
      start    : in  std_logic;
706
      reset    : in  std_logic;
707
      done     : out std_logic;
708
      -- result out
709
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
710
      r        : out std_logic_vector((width-1) downto 0)
711
    );
712
  end component sys_stage;
713 30 JonasDC
 
714
  --------------------------------------------------------------------
715
  -- sys_last_cell_logic
716
  --------------------------------------------------------------------   
717
  --    logic needed as the last piece in the systolic array pipeline
718
  --    calculates the last 2 bits of the cell_result and finishes the reduction
719
  --    also generates the result selection signal
720
  -- 
721
  component sys_last_cell_logic is
722
    port  (
723
      core_clk : in std_logic;    -- clock input
724
      reset    : in std_logic;
725
      a_0      : out std_logic;   -- a_msb for last stage
726
      cin      : in std_logic;    -- cout from last stage
727
      red_cin  : in std_logic;    -- red_cout from last stage
728
      r_sel    : out std_logic;   -- result selection bit
729
      start    : in std_logic     -- done signal from last stage
730
    );
731
  end component sys_last_cell_logic;
732 25 JonasDC
 
733
  --------------------------------------------------------------------
734 31 JonasDC
  -- sys_first_cell_logic
735
  --------------------------------------------------------------------     
736
  --    logic needed as the first piece in the systolic array pipeline
737
  --    calculates the first my_cout and generates q signal
738
  -- 
739
  component sys_first_cell_logic is
740
    port  (
741
      m0       : in std_logic;    -- lsb from m operand
742
      y0       : in std_logic;    -- lsb from y operand
743
      my_cout  : out std_logic;   -- my_cin for first stage
744
      xi       : in std_logic;    -- xi operand input
745
      xout     : out std_logic;   -- xin for first stage
746
      qout     : out std_logic;   -- qin for first stage
747
      cout     : out std_logic;   -- cin for first stage
748
      a_0      : in std_logic;    -- a_0 from first stage
749
      red_cout : out std_logic    -- red_cin for first stage
750
    );
751
  end component sys_first_cell_logic;
752
 
753
  --------------------------------------------------------------------
754 25 JonasDC
  -- sys_pipeline
755
  -------------------------------------------------------------------- 
756
  --    the pipelined systolic array for a montgommery multiplier
757
  --    contains a structural description of the pipeline using the systolic stages
758
  -- 
759
  component sys_pipeline is
760
    generic(
761
      n  : integer := 1536; -- width of the operands (# bits)
762 37 JonasDC
      t  : integer := 192;  -- total number of stages (minimum 2)
763
      tl : integer := 64;   -- lower number of stages (minimum 1)
764
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
765
                              -- if false there are no lower stages, only t counts
766 25 JonasDC
    );
767
    port(
768
      -- clock input
769
      core_clk : in  std_logic;
770
      -- modulus and y opperand input (n)-bit
771
      y        : in  std_logic_vector((n-1) downto 0);
772
      m        : in  std_logic_vector((n-1) downto 0);
773
      -- x operand input (serial)
774
      xi       : in  std_logic;
775
      next_x   : out std_logic; -- next x operand bit
776
      -- control signals
777
      start    : in  std_logic; -- start multiplier
778
      reset    : in  std_logic;
779
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
780
      -- result out
781
      r        : out std_logic_vector((n-1) downto 0)
782
    );
783
  end component sys_pipeline;
784
 
785
  component mont_multiplier is
786
  generic (
787 37 JonasDC
    n     : integer := 1536;  -- width of the operands
788
    t     : integer := 96;    -- total number of stages (minimum 2)
789
    tl    : integer := 32;    -- lower number of stages (minimum 1)
790
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
791
                              -- if false there are no lower stages, only t counts
792 25 JonasDC
  );
793
  port (
794
    -- clock input
795
    core_clk : in std_logic;
796
    -- operand inputs
797
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
798
    m        : in std_logic_vector((n-1) downto 0); -- modulus
799
    -- result output
800
    r        : out std_logic_vector((n-1) downto 0);  -- result
801
    -- control signals
802
    start    : in std_logic;
803
    reset    : in std_logic;
804
    p_sel    : in std_logic_vector(1 downto 0);
805
    load_x   : in std_logic;
806
    ready    : out std_logic
807
  );
808
  end component mont_multiplier;
809
 
810 3 JonasDC
end package mod_sim_exp_pkg;

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