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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52 37 JonasDC
  --------------------------------------------------------------------
53
  ---------------------- COMPONENT DECLARATIONS ----------------------
54
  --------------------------------------------------------------------
55
 
56
  --------------------------------------------------------------------
57 16 JonasDC
  -- d_flip_flop
58
  --------------------------------------------------------------------
59
  --    1-bit D flip-flop with asynchronous active high reset
60
  -- 
61 9 JonasDC
  component d_flip_flop is
62
    port(
63
      core_clk : in  std_logic; -- clock signal
64
      reset    : in  std_logic; -- active high reset
65
      din      : in  std_logic; -- data in
66
      dout     : out std_logic  -- data out
67 3 JonasDC
    );
68 9 JonasDC
  end component d_flip_flop;
69
 
70 16 JonasDC
  --------------------------------------------------------------------
71
  -- register_1b
72
  --------------------------------------------------------------------
73
  --    1-bit register with asynchronous reset and clock enable
74
  -- 
75 9 JonasDC
  component register_1b is
76
    port(
77
      core_clk : in  std_logic; -- clock input
78
      ce       : in  std_logic; -- clock enable (active high)
79
      reset    : in  std_logic; -- reset (active high)
80
      din      : in  std_logic; -- data in
81
      dout     : out std_logic  -- data out
82 3 JonasDC
    );
83 9 JonasDC
  end component register_1b;
84 3 JonasDC
 
85 16 JonasDC
  --------------------------------------------------------------------
86
  -- register_n
87
  --------------------------------------------------------------------
88
  --    n-bit register with asynchronous reset and clock enable
89
  -- 
90 9 JonasDC
  component register_n is
91
    generic(
92 16 JonasDC
      width : integer := 4
93 3 JonasDC
    );
94 9 JonasDC
    port(
95
      core_clk : in  std_logic; -- clock input
96
      ce       : in  std_logic; -- clock enable (active high)
97
      reset    : in  std_logic; -- reset (active high)
98 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
99
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
100 3 JonasDC
    );
101 9 JonasDC
  end component register_n;
102 3 JonasDC
 
103 16 JonasDC
  --------------------------------------------------------------------
104
  -- cell_1b_adder
105
  --------------------------------------------------------------------
106
  --    1-bit full adder cell using combinatorial logic
107
  --    
108 3 JonasDC
  component cell_1b_adder is
109
    port (
110 9 JonasDC
      -- input operands a, b
111
      a    : in  std_logic;
112
      b    : in  std_logic;
113
      -- carry in, out
114
      cin  : in  std_logic;
115
      cout : out  std_logic;
116
      -- result out
117
      r    : out  std_logic
118 3 JonasDC
    );
119
  end component cell_1b_adder;
120
 
121 16 JonasDC
  --------------------------------------------------------------------
122
  -- cell_1b_mux
123
  --------------------------------------------------------------------
124
  --    1-bit mux for a standard cell in the montgommery multiplier 
125
  --    systolic array
126
  -- 
127 3 JonasDC
  component cell_1b_mux is
128
    port (
129 9 JonasDC
      -- input bits
130
      my     : in  std_logic;
131 3 JonasDC
      y      : in  std_logic;
132
      m      : in  std_logic;
133 9 JonasDC
      -- selection bits
134 3 JonasDC
      x      : in  std_logic;
135
      q      : in  std_logic;
136 9 JonasDC
      -- mux out
137 3 JonasDC
      result : out std_logic
138
    );
139
  end component cell_1b_mux;
140
 
141 16 JonasDC
  --------------------------------------------------------------------
142
  -- cell_1b
143
  --------------------------------------------------------------------
144
  --    1-bit cell for the systolic array
145
  -- 
146 3 JonasDC
  component cell_1b is
147
    port (
148 9 JonasDC
      -- operand input bits (m+y, y and m)
149 3 JonasDC
      my   : in  std_logic;
150
      y    : in  std_logic;
151
      m    : in  std_logic;
152 16 JonasDC
      -- operand x input bit and q
153 3 JonasDC
      x    : in  std_logic;
154
      q    : in  std_logic;
155 9 JonasDC
      -- previous result input bit
156 3 JonasDC
      a    : in  std_logic;
157 9 JonasDC
      -- carry's
158 3 JonasDC
      cin  : in  std_logic;
159
      cout : out std_logic;
160 9 JonasDC
      -- cell result out
161 3 JonasDC
      r    : out std_logic
162
    );
163
  end component cell_1b;
164
 
165 16 JonasDC
  --------------------------------------------------------------------
166
  -- adder_block
167
  --------------------------------------------------------------------
168
  --    (width)-bit full adder block using cell_1b_adders with buffered
169
  --    carry out
170
  -- 
171 9 JonasDC
  component adder_block is
172
    generic (
173
      width : integer := 32 --adder operand widths
174
    );
175
    port (
176
      -- clock input
177
      core_clk : in std_logic;
178
      -- adder input operands a, b (width)-bit
179
      a : in std_logic_vector((width-1) downto 0);
180
      b : in std_logic_vector((width-1) downto 0);
181
      -- carry in, out
182
      cin   : in std_logic;
183
      cout  : out std_logic;
184
      -- adder result out (width)-bit
185
      r : out std_logic_vector((width-1) downto 0)
186
    );
187
  end component adder_block;
188
 
189 16 JonasDC
  --------------------------------------------------------------------
190 17 JonasDC
  -- standard_cell_block
191
  --------------------------------------------------------------------
192
  --    a standard cell block of (width)-bit for the montgommery multiplier 
193
  --    systolic array
194
  -- 
195
  component standard_cell_block is
196
    generic (
197
      width : integer := 16
198
    );
199
    port (
200
      -- modulus and y operand input (width)-bit
201
      my   : in  std_logic_vector((width-1) downto 0);
202
      y    : in  std_logic_vector((width-1) downto 0);
203
      m    : in  std_logic_vector((width-1) downto 0);
204
      -- q and x operand input (serial input)
205
      x    : in  std_logic;
206
      q    : in  std_logic;
207
      -- previous result in (width)-bit
208
      a    : in  std_logic_vector((width-1) downto 0);
209
      -- carry in and out
210
      cin  : in std_logic;
211
      cout : out std_logic;
212
      -- result out (width)-bit
213
      r    : out  std_logic_vector((width-1) downto 0)
214
    );
215
  end component standard_cell_block;
216
 
217
  --------------------------------------------------------------------
218 19 JonasDC
  -- counter_sync
219
  --------------------------------------------------------------------
220
  --    counter with synchronous count enable. It generates an
221
  --    overflow when max_value is reached
222
  -- 
223
  component counter_sync is
224
    generic(
225
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
226
    );
227
    port(
228
      reset_value : in integer;   -- value the counter counts to
229
      core_clk    : in std_logic; -- clock input
230
      ce          : in std_logic; -- count enable
231
      reset       : in std_logic; -- reset input
232
      overflow    : out std_logic -- gets high when counter reaches reset_value
233
    );
234
  end component counter_sync;
235 18 JonasDC
 
236 19 JonasDC
  --------------------------------------------------------------------
237
  -- stepping_logic
238
  --------------------------------------------------------------------
239
  --    stepping logic for the pipeline, generates the start pulses for the
240
  --    first stage and keeps track of when the last stages are done
241
  -- 
242
  component stepping_logic is
243
    generic(
244
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
245
      t : integer := 192    -- total nr of steps in the pipeline
246
    );
247
    port(
248
      core_clk          : in  std_logic;  -- clock input
249
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
250
      reset             : in  std_logic;  -- reset signal
251
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
252
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
253
      start_first_stage : out std_logic;  -- start pulse output for first stage
254
      stepping_done     : out std_logic   -- done signal
255
    );
256
  end component stepping_logic;
257
 
258 20 JonasDC
  --------------------------------------------------------------------
259
  -- x_shift_reg
260
  --------------------------------------------------------------------
261
  --    shift register for the x operand of the multiplier
262
  --    outputs the lsb of the register or bit at offset according to the
263
  --    selected pipeline part 
264
  -- 
265
  component x_shift_reg is
266
    generic(
267
      n  : integer := 1536; -- width of the operands (# bits)
268
      t  : integer := 48;   -- total number of stages
269
      tl : integer := 16    -- lower number of stages
270
    );
271
    port(
272
      -- clock input
273
      clk    : in  std_logic;
274
      -- x operand in (n-bit)
275
      x_in   : in  std_logic_vector((n-1) downto 0);
276
      -- control signals
277
      reset  : in  std_logic; -- reset, clears register
278
      load_x : in  std_logic; -- load operand into shift register   
279
      next_x : in  std_logic; -- next bit of x
280
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
281
      -- x operand bit out (serial)
282 21 JonasDC
      xi     : out std_logic
283 20 JonasDC
    );
284
  end component x_shift_reg;
285 23 JonasDC
 
286 24 JonasDC
  --------------------------------------------------------------------
287
  -- mod_sim_exp_core
288
  --------------------------------------------------------------------
289
  --    toplevel of the modular simultaneous exponentiation core
290
  --    contains an operand and modulus ram, multiplier, an exponent fifo
291
  --    and control logic
292
  -- 
293
  component mod_sim_exp_core is
294 43 JonasDC
    generic(
295
      C_NR_BITS_TOTAL : integer := 1536;
296
      C_NR_STAGES_TOTAL : integer := 96;
297
      C_NR_STAGES_LOW : integer := 32;
298
      C_SPLIT_PIPELINE : boolean := true
299
    );
300 24 JonasDC
    port(
301
      clk   : in  std_logic;
302
      reset : in  std_logic;
303
        -- operand memory interface (plb shared memory)
304
      write_enable : in  std_logic; -- write data to operand ram
305
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
306
      rw_address   : in  std_logic_vector (8 downto 0);   -- operand ram address bus
307
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
308
      collision    : out std_logic; -- write collision
309
        -- op_sel fifo interface
310
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
311
      fifo_push   : in  std_logic;  -- push data in exponent fifo
312
      fifo_full   : out std_logic;  -- high if fifo is full
313
      fifo_nopush : out std_logic;  -- high if error during push
314
        -- control signals
315
      start          : in  std_logic; -- start multiplication/exponentiation
316 45 JonasDC
      exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
317 24 JonasDC
      ready          : out std_logic; -- calculations done
318
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
319
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
320
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
321
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
322
      calc_time      : out std_logic
323
    );
324
  end component mod_sim_exp_core;
325
 
326 9 JonasDC
  component autorun_cntrl is
327
    port (
328
      clk              : in  std_logic;
329
      reset            : in  std_logic;
330
      start            : in  std_logic;
331
      done             : out  std_logic;
332
      op_sel           : out  std_logic_vector (1 downto 0);
333
      start_multiplier : out  std_logic;
334
      multiplier_done  : in  std_logic;
335
      read_buffer      : out  std_logic;
336
      buffer_din       : in  std_logic_vector (31 downto 0);
337
      buffer_empty     : in  std_logic
338
    );
339
  end component autorun_cntrl;
340
 
341 3 JonasDC
  component fifo_primitive is
342
    port (
343
      clk    : in  std_logic;
344
      din    : in  std_logic_vector (31 downto 0);
345
      dout   : out  std_logic_vector (31 downto 0);
346
      empty  : out  std_logic;
347
      full   : out  std_logic;
348
      push   : in  std_logic;
349
      pop    : in  std_logic;
350
      reset  : in std_logic;
351
      nopop  : out std_logic;
352
      nopush : out std_logic
353
    );
354
  end component fifo_primitive;
355
 
356
  component modulus_ram is
357
    port(
358
      clk           : in std_logic;
359
      modulus_addr  : in std_logic_vector(5 downto 0);
360
      write_modulus : in std_logic;
361
      modulus_in    : in std_logic_vector(31 downto 0);
362
      modulus_out   : out std_logic_vector(1535 downto 0)
363
    );
364
  end component modulus_ram;
365
 
366 39 JonasDC
  --------------------------------------------------------------------
367
  -- mont_ctrl
368
  --------------------------------------------------------------------
369
  --    This module controls the montgommery mutliplier and controls traffic between
370
  --    RAM and multiplier. Also contains the autorun logic for exponentiations.
371
  -- 
372 3 JonasDC
  component mont_ctrl is
373
    port (
374
      clk   : in std_logic;
375
      reset : in std_logic;
376
        -- bus side
377
      start           : in std_logic;
378
      x_sel_single    : in std_logic_vector(1 downto 0);
379
      y_sel_single    : in std_logic_vector(1 downto 0);
380
      run_auto        : in std_logic;
381
      op_buffer_empty : in std_logic;
382
      op_sel_buffer   : in std_logic_vector(31 downto 0);
383
      read_buffer     : out std_logic;
384
      done            : out std_logic;
385
      calc_time       : out std_logic;
386
        -- multiplier side
387
      op_sel           : out std_logic_vector(1 downto 0);
388
      load_x           : out std_logic;
389
      load_result      : out std_logic;
390
      start_multiplier : out std_logic;
391
      multiplier_ready : in std_logic
392
    );
393
  end component mont_ctrl;
394
 
395
  component operand_dp is
396
    port (
397
      clka  : in std_logic;
398
      wea   : in std_logic_vector(0 downto 0);
399
      addra : in std_logic_vector(5 downto 0);
400
      dina  : in std_logic_vector(31 downto 0);
401
      douta : out std_logic_vector(511 downto 0);
402
      clkb  : in std_logic;
403
      web   : in std_logic_vector(0 downto 0);
404
      addrb : in std_logic_vector(5 downto 0);
405
      dinb  : in std_logic_vector(511 downto 0);
406
      doutb : out std_logic_vector(31 downto 0)
407
    );
408
  end component operand_dp;
409
 
410
  component operand_mem is
411 39 JonasDC
    generic(
412
      n : integer := 1536
413 3 JonasDC
    );
414
    port(
415
        -- data interface (plb side)
416
      data_in    : in  std_logic_vector(31 downto 0);
417
      data_out   : out  std_logic_vector(31 downto 0);
418
      rw_address : in  std_logic_vector(8 downto 0);
419 39 JonasDC
      write_enable : in  std_logic;
420 3 JonasDC
        -- address structure:
421
        -- bit:  8   -> '1': modulus
422
        --              '0': operands
423
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
424
        --              don't care in case of modulus
425
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
426
 
427
        -- operand interface (multiplier side)
428
      op_sel    : in  std_logic_vector(1 downto 0);
429 34 JonasDC
      xy_out    : out  std_logic_vector((n-1) downto 0);
430
      m         : out  std_logic_vector((n-1) downto 0);
431
      result_in : in std_logic_vector((n-1) downto 0);
432 39 JonasDC
      -- control signals
433 3 JonasDC
      load_result    : in std_logic;
434
      result_dest_op : in std_logic_vector(1 downto 0);
435
      collision      : out std_logic;
436
        -- system clock
437
      clk : in  std_logic
438
    );
439
  end component operand_mem;
440
 
441
  component operand_ram is
442
    port( -- write_operand_ack voorzien?
443
      -- global ports
444
      clk       : in std_logic;
445
      collision : out std_logic;
446
      -- bus side connections (32-bit serial)
447
      operand_addr   : in std_logic_vector(5 downto 0);
448
      operand_in     : in std_logic_vector(31 downto 0);
449
      operand_in_sel : in std_logic_vector(1 downto 0);
450
      result_out     : out std_logic_vector(31 downto 0);
451
      write_operand  : in std_logic;
452
      -- multiplier side connections (1536 bit parallel)
453
      result_dest_op  : in std_logic_vector(1 downto 0);
454
      operand_out     : out std_logic_vector(1535 downto 0);
455
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
456
      write_result    : in std_logic;
457
      result_in       : in std_logic_vector(1535 downto 0)
458
    );
459
  end component operand_ram;
460
 
461
  component operands_sp is
462
    port (
463
      clka  : in std_logic;
464
      wea   : in std_logic_vector(0 downto 0);
465
      addra : in std_logic_vector(4 downto 0);
466
      dina  : in std_logic_vector(31 downto 0);
467
      douta : out std_logic_vector(511 downto 0)
468
    );
469
  end component operands_sp;
470
 
471 25 JonasDC
 
472
  component sys_stage is
473
    generic(
474
      width : integer := 32 -- width of the stage
475
    );
476
    port(
477
      -- clock input
478
      core_clk : in  std_logic;
479
      -- modulus and y operand input (width)-bit
480
      y        : in  std_logic_vector((width-1) downto 0);
481
      m        : in  std_logic_vector((width) downto 0);
482
      my_cin   : in  std_logic;
483
      my_cout  : out std_logic;
484
      -- q and x operand input (serial input)
485
      xin      : in  std_logic;
486
      qin      : in  std_logic;
487
      -- q and x operand output (serial output)
488
      xout     : out std_logic;
489
      qout     : out std_logic;
490
      -- msb input (lsb from next stage, for shift right operation)
491
      a_msb    : in  std_logic;
492
      a_0      : out std_logic;
493
      -- carry out(clocked) and in
494
      cin      : in  std_logic;
495
      cout     : out std_logic;
496
      -- reduction adder carry's
497
      red_cin  : in std_logic;
498
      red_cout : out std_logic;
499
      -- control singals
500
      start    : in  std_logic;
501
      reset    : in  std_logic;
502
      done     : out std_logic;
503
      -- result out
504
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
505
      r        : out std_logic_vector((width-1) downto 0)
506
    );
507
  end component sys_stage;
508 30 JonasDC
 
509
  --------------------------------------------------------------------
510
  -- sys_last_cell_logic
511
  --------------------------------------------------------------------   
512
  --    logic needed as the last piece in the systolic array pipeline
513
  --    calculates the last 2 bits of the cell_result and finishes the reduction
514
  --    also generates the result selection signal
515
  -- 
516
  component sys_last_cell_logic is
517
    port  (
518
      core_clk : in std_logic;    -- clock input
519
      reset    : in std_logic;
520
      a_0      : out std_logic;   -- a_msb for last stage
521
      cin      : in std_logic;    -- cout from last stage
522
      red_cin  : in std_logic;    -- red_cout from last stage
523
      r_sel    : out std_logic;   -- result selection bit
524
      start    : in std_logic     -- done signal from last stage
525
    );
526
  end component sys_last_cell_logic;
527 25 JonasDC
 
528
  --------------------------------------------------------------------
529 31 JonasDC
  -- sys_first_cell_logic
530
  --------------------------------------------------------------------     
531
  --    logic needed as the first piece in the systolic array pipeline
532
  --    calculates the first my_cout and generates q signal
533
  -- 
534
  component sys_first_cell_logic is
535
    port  (
536
      m0       : in std_logic;    -- lsb from m operand
537
      y0       : in std_logic;    -- lsb from y operand
538
      my_cout  : out std_logic;   -- my_cin for first stage
539
      xi       : in std_logic;    -- xi operand input
540
      xout     : out std_logic;   -- xin for first stage
541
      qout     : out std_logic;   -- qin for first stage
542
      cout     : out std_logic;   -- cin for first stage
543
      a_0      : in std_logic;    -- a_0 from first stage
544
      red_cout : out std_logic    -- red_cin for first stage
545
    );
546
  end component sys_first_cell_logic;
547
 
548
  --------------------------------------------------------------------
549 25 JonasDC
  -- sys_pipeline
550
  -------------------------------------------------------------------- 
551
  --    the pipelined systolic array for a montgommery multiplier
552
  --    contains a structural description of the pipeline using the systolic stages
553
  -- 
554
  component sys_pipeline is
555
    generic(
556
      n  : integer := 1536; -- width of the operands (# bits)
557 37 JonasDC
      t  : integer := 192;  -- total number of stages (minimum 2)
558
      tl : integer := 64;   -- lower number of stages (minimum 1)
559
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
560
                              -- if false there are no lower stages, only t counts
561 25 JonasDC
    );
562
    port(
563
      -- clock input
564
      core_clk : in  std_logic;
565
      -- modulus and y opperand input (n)-bit
566
      y        : in  std_logic_vector((n-1) downto 0);
567
      m        : in  std_logic_vector((n-1) downto 0);
568
      -- x operand input (serial)
569
      xi       : in  std_logic;
570
      next_x   : out std_logic; -- next x operand bit
571
      -- control signals
572
      start    : in  std_logic; -- start multiplier
573
      reset    : in  std_logic;
574
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
575
      -- result out
576
      r        : out std_logic_vector((n-1) downto 0)
577
    );
578
  end component sys_pipeline;
579
 
580
  component mont_multiplier is
581
  generic (
582 37 JonasDC
    n     : integer := 1536;  -- width of the operands
583
    t     : integer := 96;    -- total number of stages (minimum 2)
584
    tl    : integer := 32;    -- lower number of stages (minimum 1)
585
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
586
                              -- if false there are no lower stages, only t counts
587 25 JonasDC
  );
588
  port (
589
    -- clock input
590
    core_clk : in std_logic;
591
    -- operand inputs
592
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
593
    m        : in std_logic_vector((n-1) downto 0); -- modulus
594
    -- result output
595
    r        : out std_logic_vector((n-1) downto 0);  -- result
596
    -- control signals
597
    start    : in std_logic;
598
    reset    : in std_logic;
599
    p_sel    : in std_logic_vector(1 downto 0);
600
    load_x   : in std_logic;
601
    ready    : out std_logic
602
  );
603
  end component mont_multiplier;
604
 
605 3 JonasDC
end package mod_sim_exp_pkg;

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