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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 63 JonasDC
library mod_sim_exp;
51
use mod_sim_exp.std_functions.all;
52 9 JonasDC
 
53 3 JonasDC
package mod_sim_exp_pkg is
54 37 JonasDC
  --------------------------------------------------------------------
55
  ---------------------- COMPONENT DECLARATIONS ----------------------
56
  --------------------------------------------------------------------
57
 
58 63 JonasDC
  --------------------------- MULTIPLIER -----------------------------
59
 
60 37 JonasDC
  --------------------------------------------------------------------
61 16 JonasDC
  -- d_flip_flop
62
  --------------------------------------------------------------------
63
  --    1-bit D flip-flop with asynchronous active high reset
64
  -- 
65 9 JonasDC
  component d_flip_flop is
66
    port(
67
      core_clk : in  std_logic; -- clock signal
68
      reset    : in  std_logic; -- active high reset
69
      din      : in  std_logic; -- data in
70
      dout     : out std_logic  -- data out
71 3 JonasDC
    );
72 9 JonasDC
  end component d_flip_flop;
73
 
74 16 JonasDC
  --------------------------------------------------------------------
75
  -- register_1b
76
  --------------------------------------------------------------------
77
  --    1-bit register with asynchronous reset and clock enable
78
  -- 
79 9 JonasDC
  component register_1b is
80
    port(
81
      core_clk : in  std_logic; -- clock input
82
      ce       : in  std_logic; -- clock enable (active high)
83
      reset    : in  std_logic; -- reset (active high)
84
      din      : in  std_logic; -- data in
85
      dout     : out std_logic  -- data out
86 3 JonasDC
    );
87 9 JonasDC
  end component register_1b;
88 3 JonasDC
 
89 16 JonasDC
  --------------------------------------------------------------------
90
  -- register_n
91
  --------------------------------------------------------------------
92
  --    n-bit register with asynchronous reset and clock enable
93
  -- 
94 9 JonasDC
  component register_n is
95
    generic(
96 16 JonasDC
      width : integer := 4
97 3 JonasDC
    );
98 9 JonasDC
    port(
99
      core_clk : in  std_logic; -- clock input
100
      ce       : in  std_logic; -- clock enable (active high)
101
      reset    : in  std_logic; -- reset (active high)
102 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
103
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
104 3 JonasDC
    );
105 9 JonasDC
  end component register_n;
106 3 JonasDC
 
107 16 JonasDC
  --------------------------------------------------------------------
108
  -- cell_1b_adder
109
  --------------------------------------------------------------------
110
  --    1-bit full adder cell using combinatorial logic
111
  --    
112 3 JonasDC
  component cell_1b_adder is
113
    port (
114 9 JonasDC
      -- input operands a, b
115
      a    : in  std_logic;
116
      b    : in  std_logic;
117
      -- carry in, out
118
      cin  : in  std_logic;
119
      cout : out  std_logic;
120
      -- result out
121
      r    : out  std_logic
122 3 JonasDC
    );
123
  end component cell_1b_adder;
124
 
125 16 JonasDC
  --------------------------------------------------------------------
126
  -- cell_1b_mux
127
  --------------------------------------------------------------------
128
  --    1-bit mux for a standard cell in the montgommery multiplier 
129
  --    systolic array
130
  -- 
131 3 JonasDC
  component cell_1b_mux is
132
    port (
133 9 JonasDC
      -- input bits
134
      my     : in  std_logic;
135 3 JonasDC
      y      : in  std_logic;
136
      m      : in  std_logic;
137 9 JonasDC
      -- selection bits
138 3 JonasDC
      x      : in  std_logic;
139
      q      : in  std_logic;
140 9 JonasDC
      -- mux out
141 3 JonasDC
      result : out std_logic
142
    );
143
  end component cell_1b_mux;
144
 
145 16 JonasDC
  --------------------------------------------------------------------
146
  -- cell_1b
147
  --------------------------------------------------------------------
148
  --    1-bit cell for the systolic array
149
  -- 
150 3 JonasDC
  component cell_1b is
151
    port (
152 9 JonasDC
      -- operand input bits (m+y, y and m)
153 3 JonasDC
      my   : in  std_logic;
154
      y    : in  std_logic;
155
      m    : in  std_logic;
156 16 JonasDC
      -- operand x input bit and q
157 3 JonasDC
      x    : in  std_logic;
158
      q    : in  std_logic;
159 9 JonasDC
      -- previous result input bit
160 3 JonasDC
      a    : in  std_logic;
161 9 JonasDC
      -- carry's
162 3 JonasDC
      cin  : in  std_logic;
163
      cout : out std_logic;
164 9 JonasDC
      -- cell result out
165 3 JonasDC
      r    : out std_logic
166
    );
167
  end component cell_1b;
168
 
169 16 JonasDC
  --------------------------------------------------------------------
170
  -- adder_block
171
  --------------------------------------------------------------------
172
  --    (width)-bit full adder block using cell_1b_adders with buffered
173
  --    carry out
174
  -- 
175 9 JonasDC
  component adder_block is
176
    generic (
177
      width : integer := 32 --adder operand widths
178
    );
179
    port (
180
      -- clock input
181
      core_clk : in std_logic;
182
      -- adder input operands a, b (width)-bit
183
      a : in std_logic_vector((width-1) downto 0);
184
      b : in std_logic_vector((width-1) downto 0);
185
      -- carry in, out
186
      cin   : in std_logic;
187
      cout  : out std_logic;
188
      -- adder result out (width)-bit
189
      r : out std_logic_vector((width-1) downto 0)
190
    );
191
  end component adder_block;
192
 
193 16 JonasDC
  --------------------------------------------------------------------
194 17 JonasDC
  -- standard_cell_block
195
  --------------------------------------------------------------------
196
  --    a standard cell block of (width)-bit for the montgommery multiplier 
197
  --    systolic array
198
  -- 
199
  component standard_cell_block is
200
    generic (
201
      width : integer := 16
202
    );
203
    port (
204
      -- modulus and y operand input (width)-bit
205
      my   : in  std_logic_vector((width-1) downto 0);
206
      y    : in  std_logic_vector((width-1) downto 0);
207
      m    : in  std_logic_vector((width-1) downto 0);
208
      -- q and x operand input (serial input)
209
      x    : in  std_logic;
210
      q    : in  std_logic;
211
      -- previous result in (width)-bit
212
      a    : in  std_logic_vector((width-1) downto 0);
213
      -- carry in and out
214
      cin  : in std_logic;
215
      cout : out std_logic;
216
      -- result out (width)-bit
217
      r    : out  std_logic_vector((width-1) downto 0)
218
    );
219
  end component standard_cell_block;
220
 
221
  --------------------------------------------------------------------
222 19 JonasDC
  -- counter_sync
223
  --------------------------------------------------------------------
224
  --    counter with synchronous count enable. It generates an
225
  --    overflow when max_value is reached
226
  -- 
227
  component counter_sync is
228
    generic(
229
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
230
    );
231
    port(
232
      reset_value : in integer;   -- value the counter counts to
233
      core_clk    : in std_logic; -- clock input
234
      ce          : in std_logic; -- count enable
235
      reset       : in std_logic; -- reset input
236
      overflow    : out std_logic -- gets high when counter reaches reset_value
237
    );
238
  end component counter_sync;
239 18 JonasDC
 
240 19 JonasDC
  --------------------------------------------------------------------
241
  -- stepping_logic
242
  --------------------------------------------------------------------
243
  --    stepping logic for the pipeline, generates the start pulses for the
244
  --    first stage and keeps track of when the last stages are done
245
  -- 
246
  component stepping_logic is
247
    generic(
248
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
249
      t : integer := 192    -- total nr of steps in the pipeline
250
    );
251
    port(
252
      core_clk          : in  std_logic;  -- clock input
253
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
254
      reset             : in  std_logic;  -- reset signal
255
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
256
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
257
      start_first_stage : out std_logic;  -- start pulse output for first stage
258
      stepping_done     : out std_logic   -- done signal
259
    );
260
  end component stepping_logic;
261
 
262 20 JonasDC
  --------------------------------------------------------------------
263
  -- x_shift_reg
264
  --------------------------------------------------------------------
265
  --    shift register for the x operand of the multiplier
266
  --    outputs the lsb of the register or bit at offset according to the
267
  --    selected pipeline part 
268
  -- 
269
  component x_shift_reg is
270
    generic(
271
      n  : integer := 1536; -- width of the operands (# bits)
272
      t  : integer := 48;   -- total number of stages
273
      tl : integer := 16    -- lower number of stages
274
    );
275
    port(
276
      -- clock input
277
      clk    : in  std_logic;
278
      -- x operand in (n-bit)
279
      x_in   : in  std_logic_vector((n-1) downto 0);
280
      -- control signals
281
      reset  : in  std_logic; -- reset, clears register
282
      load_x : in  std_logic; -- load operand into shift register   
283
      next_x : in  std_logic; -- next bit of x
284
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
285
      -- x operand bit out (serial)
286 21 JonasDC
      xi     : out std_logic
287 20 JonasDC
    );
288
  end component x_shift_reg;
289 63 JonasDC
 
290 9 JonasDC
  component autorun_cntrl is
291
    port (
292
      clk              : in  std_logic;
293
      reset            : in  std_logic;
294
      start            : in  std_logic;
295
      done             : out  std_logic;
296
      op_sel           : out  std_logic_vector (1 downto 0);
297
      start_multiplier : out  std_logic;
298
      multiplier_done  : in  std_logic;
299
      read_buffer      : out  std_logic;
300
      buffer_din       : in  std_logic_vector (31 downto 0);
301
      buffer_empty     : in  std_logic
302
    );
303
  end component autorun_cntrl;
304
 
305 39 JonasDC
  --------------------------------------------------------------------
306
  -- mont_ctrl
307
  --------------------------------------------------------------------
308
  --    This module controls the montgommery mutliplier and controls traffic between
309
  --    RAM and multiplier. Also contains the autorun logic for exponentiations.
310
  -- 
311 3 JonasDC
  component mont_ctrl is
312
    port (
313
      clk   : in std_logic;
314
      reset : in std_logic;
315
        -- bus side
316
      start           : in std_logic;
317
      x_sel_single    : in std_logic_vector(1 downto 0);
318
      y_sel_single    : in std_logic_vector(1 downto 0);
319
      run_auto        : in std_logic;
320
      op_buffer_empty : in std_logic;
321
      op_sel_buffer   : in std_logic_vector(31 downto 0);
322
      read_buffer     : out std_logic;
323
      done            : out std_logic;
324
      calc_time       : out std_logic;
325
        -- multiplier side
326
      op_sel           : out std_logic_vector(1 downto 0);
327
      load_x           : out std_logic;
328
      load_result      : out std_logic;
329
      start_multiplier : out std_logic;
330
      multiplier_ready : in std_logic
331
    );
332
  end component mont_ctrl;
333
 
334 25 JonasDC
  component sys_stage is
335
    generic(
336
      width : integer := 32 -- width of the stage
337
    );
338
    port(
339
      -- clock input
340
      core_clk : in  std_logic;
341
      -- modulus and y operand input (width)-bit
342
      y        : in  std_logic_vector((width-1) downto 0);
343
      m        : in  std_logic_vector((width) downto 0);
344
      my_cin   : in  std_logic;
345
      my_cout  : out std_logic;
346
      -- q and x operand input (serial input)
347
      xin      : in  std_logic;
348
      qin      : in  std_logic;
349
      -- q and x operand output (serial output)
350
      xout     : out std_logic;
351
      qout     : out std_logic;
352
      -- msb input (lsb from next stage, for shift right operation)
353
      a_msb    : in  std_logic;
354
      a_0      : out std_logic;
355
      -- carry out(clocked) and in
356
      cin      : in  std_logic;
357
      cout     : out std_logic;
358
      -- reduction adder carry's
359
      red_cin  : in std_logic;
360
      red_cout : out std_logic;
361
      -- control singals
362
      start    : in  std_logic;
363
      reset    : in  std_logic;
364
      done     : out std_logic;
365
      -- result out
366
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
367
      r        : out std_logic_vector((width-1) downto 0)
368
    );
369
  end component sys_stage;
370 30 JonasDC
 
371
  --------------------------------------------------------------------
372
  -- sys_last_cell_logic
373
  --------------------------------------------------------------------   
374
  --    logic needed as the last piece in the systolic array pipeline
375
  --    calculates the last 2 bits of the cell_result and finishes the reduction
376
  --    also generates the result selection signal
377
  -- 
378
  component sys_last_cell_logic is
379
    port  (
380
      core_clk : in std_logic;    -- clock input
381
      reset    : in std_logic;
382
      a_0      : out std_logic;   -- a_msb for last stage
383
      cin      : in std_logic;    -- cout from last stage
384
      red_cin  : in std_logic;    -- red_cout from last stage
385
      r_sel    : out std_logic;   -- result selection bit
386
      start    : in std_logic     -- done signal from last stage
387
    );
388
  end component sys_last_cell_logic;
389 25 JonasDC
 
390
  --------------------------------------------------------------------
391 31 JonasDC
  -- sys_first_cell_logic
392
  --------------------------------------------------------------------     
393
  --    logic needed as the first piece in the systolic array pipeline
394
  --    calculates the first my_cout and generates q signal
395
  -- 
396
  component sys_first_cell_logic is
397
    port  (
398
      m0       : in std_logic;    -- lsb from m operand
399
      y0       : in std_logic;    -- lsb from y operand
400
      my_cout  : out std_logic;   -- my_cin for first stage
401
      xi       : in std_logic;    -- xi operand input
402
      xout     : out std_logic;   -- xin for first stage
403
      qout     : out std_logic;   -- qin for first stage
404
      cout     : out std_logic;   -- cin for first stage
405
      a_0      : in std_logic;    -- a_0 from first stage
406
      red_cout : out std_logic    -- red_cin for first stage
407
    );
408
  end component sys_first_cell_logic;
409
 
410
  --------------------------------------------------------------------
411 25 JonasDC
  -- sys_pipeline
412
  -------------------------------------------------------------------- 
413
  --    the pipelined systolic array for a montgommery multiplier
414
  --    contains a structural description of the pipeline using the systolic stages
415
  -- 
416
  component sys_pipeline is
417
    generic(
418
      n  : integer := 1536; -- width of the operands (# bits)
419 37 JonasDC
      t  : integer := 192;  -- total number of stages (minimum 2)
420
      tl : integer := 64;   -- lower number of stages (minimum 1)
421
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
422
                              -- if false there are no lower stages, only t counts
423 25 JonasDC
    );
424
    port(
425
      -- clock input
426
      core_clk : in  std_logic;
427
      -- modulus and y opperand input (n)-bit
428
      y        : in  std_logic_vector((n-1) downto 0);
429
      m        : in  std_logic_vector((n-1) downto 0);
430
      -- x operand input (serial)
431
      xi       : in  std_logic;
432
      next_x   : out std_logic; -- next x operand bit
433
      -- control signals
434
      start    : in  std_logic; -- start multiplier
435
      reset    : in  std_logic;
436
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
437
      -- result out
438
      r        : out std_logic_vector((n-1) downto 0)
439
    );
440
  end component sys_pipeline;
441
 
442
  component mont_multiplier is
443
  generic (
444 37 JonasDC
    n     : integer := 1536;  -- width of the operands
445
    t     : integer := 96;    -- total number of stages (minimum 2)
446
    tl    : integer := 32;    -- lower number of stages (minimum 1)
447
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
448
                              -- if false there are no lower stages, only t counts
449 25 JonasDC
  );
450
  port (
451
    -- clock input
452
    core_clk : in std_logic;
453
    -- operand inputs
454
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
455
    m        : in std_logic_vector((n-1) downto 0); -- modulus
456
    -- result output
457
    r        : out std_logic_vector((n-1) downto 0);  -- result
458
    -- control signals
459
    start    : in std_logic;
460
    reset    : in std_logic;
461
    p_sel    : in std_logic_vector(1 downto 0);
462
    load_x   : in std_logic;
463
    ready    : out std_logic
464
  );
465
  end component mont_multiplier;
466 63 JonasDC
 
467
 
468
  ------------------------------ MEMORY ------------------------------
469 25 JonasDC
 
470 69 JonasDC
  -------------------------- xil_prim specific -----------------------
471 63 JonasDC
  --------------------------------------------------------------------
472
  -- operand_dp
473
  --------------------------------------------------------------------
474
  --    true dual port RAM 512x4, uses xilinx primitives
475
  --
476
  component operand_dp is
477
    port (
478
      clka  : in std_logic;
479
      wea   : in std_logic_vector(0 downto 0);
480
      addra : in std_logic_vector(5 downto 0);
481
      dina  : in std_logic_vector(31 downto 0);
482
      douta : out std_logic_vector(511 downto 0);
483
      clkb  : in std_logic;
484
      web   : in std_logic_vector(0 downto 0);
485
      addrb : in std_logic_vector(5 downto 0);
486
      dinb  : in std_logic_vector(511 downto 0);
487
      doutb : out std_logic_vector(31 downto 0)
488
    );
489
  end component operand_dp;
490
 
491
  --------------------------------------------------------------------
492
  -- operand_sp
493
  --------------------------------------------------------------------
494
  --    dual port RAM 512x2, uses xilinx primitives
495
  --
496
  component operands_sp is
497
    port (
498
      clka  : in std_logic;
499
      wea   : in std_logic_vector(0 downto 0);
500
      addra : in std_logic_vector(4 downto 0);
501
      dina  : in std_logic_vector(31 downto 0);
502
      douta : out std_logic_vector(511 downto 0)
503
    );
504
  end component operands_sp;
505
 
506
  --------------------------------------------------------------------
507 69 JonasDC
  -- fifo_primitive
508
  --------------------------------------------------------------------
509
  --    a xilinx fifo primitive wrapper
510
  -- 
511
  component fifo_primitive is
512
    port (
513
      clk    : in  std_logic;
514
      din    : in  std_logic_vector (31 downto 0);
515
      dout   : out  std_logic_vector (31 downto 0);
516
      empty  : out  std_logic;
517
      full   : out  std_logic;
518
      push   : in  std_logic;
519
      pop    : in  std_logic;
520
      reset  : in std_logic;
521
      nopop  : out std_logic;
522
      nopush : out std_logic
523
    );
524
  end component fifo_primitive;
525
 
526
  --------------------------------------------------------------------
527
  -- operand_ram
528
  --------------------------------------------------------------------
529
  --    RAM for the operands, fixed width of 1536-bit and depth of 4
530
  --    uses xilinx primitives
531
  --
532
  component operand_ram is
533
    port(
534
      -- global ports
535
      clk       : in std_logic;
536
      collision : out std_logic;
537
      -- bus side connections (32-bit serial)
538
      operand_addr   : in std_logic_vector(5 downto 0);
539
      operand_in     : in std_logic_vector(31 downto 0);
540
      operand_in_sel : in std_logic_vector(1 downto 0);
541
      result_out     : out std_logic_vector(31 downto 0);
542
      write_operand  : in std_logic;
543
      -- multiplier side connections (1536 bit parallel)
544
      result_dest_op  : in std_logic_vector(1 downto 0);
545
      operand_out     : out std_logic_vector(1535 downto 0);
546
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
547
      write_result    : in std_logic;
548
      result_in       : in std_logic_vector(1535 downto 0)
549
    );
550
  end component operand_ram;
551
 
552
  --------------------------------------------------------------------
553
  -- modulus_ram
554
  --------------------------------------------------------------------
555
  --    RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives
556
  --
557
  component modulus_ram is
558
    port(
559
      clk           : in std_logic;
560
      modulus_addr  : in std_logic_vector(5 downto 0);
561
      write_modulus : in std_logic;
562
      modulus_in    : in std_logic_vector(31 downto 0);
563
      modulus_out   : out std_logic_vector(1535 downto 0)
564
    );
565
  end component modulus_ram;
566
 
567
 
568
  ------------------------- generic modules --------------------------
569
 
570
  --------------------------------------------------------------------
571 63 JonasDC
  -- dpram_generic
572
  --------------------------------------------------------------------
573
  --    behavorial description of a dual port ram with one 32-bit
574
  --    write port and one 32-bit read port
575
  -- 
576
  component dpram_generic is
577
    generic (
578
      depth : integer := 2
579
    );
580
    port  (
581
      clk : in std_logic;
582
      -- write port
583
      waddr : in std_logic_vector(log2(depth)-1 downto 0);
584
      we    : in std_logic;
585
      din   : in std_logic_vector(31 downto 0);
586
      -- read port
587
      raddr : in std_logic_vector(log2(depth)-1 downto 0);
588
      dout  : out std_logic_vector(31 downto 0)
589
    );
590
  end component dpram_generic;
591
 
592
  --------------------------------------------------------------------
593
  -- tdpram_generic
594
  --------------------------------------------------------------------
595
  --    behavorial description of a true dual port ram with 2
596
  --    32-bit write/read ports
597
  -- 
598
  component tdpram_generic is
599
    generic (
600
      depth : integer := 9
601
    );
602
    port (
603
      -- port A
604
      clkA  : in std_logic;
605
      addrA : in std_logic_vector(log2(depth)-1 downto 0);
606
      weA   : in std_logic;
607
      dinA  : in std_logic_vector(31 downto 0);
608
      doutA : out std_logic_vector(31 downto 0);
609
      -- port B
610
      clkB  : in std_logic;
611
      addrB : in std_logic_vector(log2(depth)-1 downto 0);
612
      weB   : in std_logic;
613
      dinB  : in std_logic_vector(31 downto 0);
614
      doutB : out std_logic_vector(31 downto 0)
615
    );
616
  end component tdpram_generic;
617
 
618
  --------------------------------------------------------------------
619
  -- fifo_generic
620
  --------------------------------------------------------------------
621
  --    a behavorial implementation of a fifo that is designed to 
622
  --    infer blockram
623
  -- 
624
  component fifo_generic is
625
    generic (
626
      depth : integer := 32
627
    );
628
    port  (
629
      clk    : in  std_logic; -- clock input
630
      din    : in  std_logic_vector (31 downto 0); -- 32 bit input data for push
631
      dout   : out  std_logic_vector (31 downto 0); -- 32 bit output data for pop
632
      empty  : out  std_logic; -- empty flag, 1 when FIFO is empty
633
      full   : out  std_logic; -- full flag, 1 when FIFO is full
634
      push   : in  std_logic;
635
      pop    : in  std_logic;
636
      reset  : in std_logic;
637
      nopop  : out std_logic;
638
      nopush : out std_logic
639
    );
640
  end component fifo_generic;
641
 
642
  --------------------------------------------------------------------
643
  -- modulus_ram_gen
644
  --------------------------------------------------------------------
645 69 JonasDC
  --    structural description of a RAM to hold the modulus, with 
646 63 JonasDC
  --    adjustable width and depth(nr of moduluses)
647
  --
648
  component modulus_ram_gen is
649
    generic(
650
      width : integer := 1536;  -- must be a multiple of 32
651
      depth : integer := 2      -- nr of moduluses
652
    );
653
    port(
654
      clk            : in std_logic;
655
        -- bus side
656
      write_modulus  : in std_logic; -- write enable
657
      modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
658
      modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
659
      modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
660
      modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
661
        -- multiplier side
662
      modulus_out    : out std_logic_vector(width-1 downto 0)
663
    );
664
  end component modulus_ram_gen;
665
 
666
  --------------------------------------------------------------------
667
  -- operand_ram_gen
668
  --------------------------------------------------------------------
669
  --    behavorial description of a RAM to hold the operands, with 
670
  --    adjustable width and depth(nr of operands)
671
  --
672
  component operand_ram_gen is
673
    generic(
674
      width : integer := 1536; -- width of the operands
675
      depth : integer := 4     -- nr of operands
676
    );
677
    port(
678
        -- global ports
679
      clk       : in std_logic;
680
      collision : out std_logic; -- 1 if simultaneous write on RAM
681
        -- bus side connections (32-bit serial)
682
      write_operand  : in std_logic; -- write_enable
683
      operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
684
      operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
685
      operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
686
      result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
687
      operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
688
        -- multiplier side connections (width-bit parallel)
689
      result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
690
      operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
691
      write_result    : in std_logic; -- write enable for multiplier side
692
      result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
693
    );
694
  end component operand_ram_gen;
695
 
696 69 JonasDC
 
697
 
698
  ------------------------ asymmetric modules ------------------------
699
 
700 63 JonasDC
  --------------------------------------------------------------------
701 69 JonasDC
  -- dpram_asym
702 63 JonasDC
  --------------------------------------------------------------------
703 69 JonasDC
  --    behavorial description of an asymmetric dual port ram
704
  --    with one (wrwidth)-bit write port and one 32-bit read
705
  --    port. Made using the templates of xilinx and altera for
706
  --    asymmetric ram.
707 63 JonasDC
  --
708 69 JonasDC
  component dpram_asym is
709
    generic(
710
      rddepth : integer := 4; -- nr of 32-bit words
711
      wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
712
      device  : string  := "xilinx"  -- device template to use
713 63 JonasDC
    );
714 69 JonasDC
    port(
715
      clk : in std_logic;
716
      -- write port
717
      waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
718
      we    : in std_logic;
719
      din   : in std_logic_vector(wrwidth-1 downto 0);
720
      -- read port
721
      raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
722
      dout  : out std_logic_vector(31 downto 0)
723
    );
724
  end component dpram_asym;
725 63 JonasDC
 
726 69 JonasDC
  --------------------------------------------------------------------
727
  -- dpramblock_asym
728
  --------------------------------------------------------------------
729
  --    structural description of an asymmetric dual port ram
730
  --    with one 32-bit write port and one (width)-bit read
731
  --    port.
732
  -- 
733
  component dpramblock_asym is
734
    generic(
735
      width  : integer := 256;  -- read width
736
      depth  : integer := 2;    -- nr of (width)-bit words
737
      device : string  := "xilinx"
738
    );
739
    port(
740
      clk : in std_logic;
741
      -- write port
742
      waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
743
      we    : in std_logic;
744
      din   : in std_logic_vector(31 downto 0);
745
      -- read port
746
      raddr : in std_logic_vector(log2(depth)-1 downto 0);
747
      dout  : out std_logic_vector(width-1 downto 0)
748
    );
749
  end component dpramblock_asym;
750 63 JonasDC
 
751 69 JonasDC
  --------------------------------------------------------------------
752
  -- tdpram_asym
753
  --------------------------------------------------------------------
754
  --    behavorial description of an asymmetric true dual port
755
  --    ram with one (widthA)-bit read/write port and one 32-bit
756
  --    read/write port. Made using the templates of xilinx and
757
  --    altera for asymmetric ram.
758
  --
759
  component tdpram_asym is
760 63 JonasDC
    generic(
761 69 JonasDC
      depthB : integer := 4; -- nr of 32-bit words
762
      widthA : integer := 2;  -- port A width, must be smaller than or equal to 32
763
      device : string  := "xilinx"
764 63 JonasDC
    );
765
    port(
766 69 JonasDC
      clk : in std_logic;
767
      -- port A (widthA)-bit
768
      addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
769
      weA   : in std_logic;
770
      dinA  : in std_logic_vector(widthA-1 downto 0);
771
      doutA : out std_logic_vector(widthA-1 downto 0);
772
      -- port B 32-bit
773
      addrB : in std_logic_vector(log2(depthB)-1 downto 0);
774
      weB   : in std_logic;
775
      dinB  : in std_logic_vector(31 downto 0);
776
      doutB : out std_logic_vector(31 downto 0)
777
    );
778
  end component tdpram_asym;
779 63 JonasDC
 
780 69 JonasDC
  --------------------------------------------------------------------
781
  -- tdpramblock_asym
782
  --------------------------------------------------------------------
783
  --    structural description of an asymmetric true dual port
784
  --    ram with one 32-bit read/write port and one (width)-bit
785
  --    read/write port.
786
  --
787
  component tdpramblock_asym is
788
    generic (
789
      depth  : integer := 4;    -- nr of (width)-bit words
790
      width  : integer := 512;  -- width of portB
791
      device : string  := "xilinx"
792 63 JonasDC
    );
793 69 JonasDC
    port  (
794
      clk : in std_logic;
795
      -- port A 32-bit
796
      addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
797
      weA   : in std_logic;
798
      dinA  : in std_logic_vector(31 downto 0);
799
      doutA : out std_logic_vector(31 downto 0);
800
      -- port B (width)-bit
801
      addrB : in std_logic_vector(log2(depth)-1 downto 0);
802
      weB   : in std_logic;
803
      dinB  : in std_logic_vector(width-1 downto 0);
804
      doutB : out std_logic_vector(width-1 downto 0)
805
    );
806
  end component tdpramblock_asym;
807 63 JonasDC
 
808
  --------------------------------------------------------------------
809 69 JonasDC
  -- modulus_ram_asym
810 63 JonasDC
  --------------------------------------------------------------------
811 69 JonasDC
  --    BRAM memory and logic to store the modulus, due to the
812
  --    achitecture, a minimum depth of 2 is needed for this
813
  --    module to be inferred into blockram, this version is
814
  --    slightly more performant than modulus_ram_gen and uses
815
  --    less resources. but does not work on every fpga, only
816
  --    the ones that support asymmetric rams.
817 63 JonasDC
  --
818 69 JonasDC
  component modulus_ram_asym is
819
    generic(
820
      width : integer := 1536;  -- must be a multiple of 32
821
      depth : integer := 2;     -- nr of moduluses
822
      device : string := "xilinx"
823
    );
824
    port(
825
      clk            : in std_logic;
826
        -- bus side
827
      write_modulus  : in std_logic; -- write enable
828
      modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
829
      modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
830
      modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
831
      modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
832
        -- multiplier side
833
      modulus_out    : out std_logic_vector(width-1 downto 0)
834
    );
835
  end component modulus_ram_asym;
836
 
837
  --------------------------------------------------------------------
838
  -- operand_ram_asym
839
  --------------------------------------------------------------------
840
  --    BRAM memory and logic to store the operands, due to the
841
  --    achitecture, a minimum depth of 2 is needed for this
842
  --    module to be inferred into blockram, this version is
843
  --    slightly more performant than operand_ram_gen and uses
844
  --    less resources. but does not work on every fpga, only
845
  --    the ones that support asymmetric rams. 
846
  --
847
  component operand_ram_asym is
848
    generic(
849
      width  : integer := 1536; -- width of the operands
850
      depth  : integer := 4;    -- nr of operands
851
      device : string  := "xilinx"
852
    );
853
    port(
854
        -- global ports
855
      clk       : in std_logic;
856
      collision : out std_logic; -- 1 if simultaneous write on RAM
857
        -- bus side connections (32-bit serial)
858
      write_operand  : in std_logic; -- write_enable
859
      operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
860
      operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
861
      operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
862
      result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
863
      operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
864
        -- multiplier side connections (width-bit parallel)
865
      result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
866
      operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
867
      write_result    : in std_logic; -- write enable for multiplier side
868
      result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
869
    );
870
  end component operand_ram_asym;
871
 
872
  --------------------------------------------------------------------
873
  -- operand_mem
874
  --------------------------------------------------------------------
875
  --    RAM memory and logic to the store operands and the
876
  --    modulus for the montgomery multiplier, the user has a
877
  --    choise between 3 memory styles, more detail in the
878
  --    documentation.
879
  --
880 63 JonasDC
  --    address structure:
881
  --    bit: highest   ->  '1': modulus
882
  --                       '0': operands
883
  --    bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
884 69 JonasDC
  --                                        modulus_in_sel in case of highest bit = '1'
885 63 JonasDC
  --    bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
886
  -- 
887 69 JonasDC
  component operand_mem is
888 63 JonasDC
    generic(
889 69 JonasDC
      width     : integer := 1536; -- width of the operands
890
      nr_op     : integer := 4; -- nr of operand storages, has to be greater than nr_m
891
      nr_m      : integer := 2; -- nr of modulus storages
892
      mem_style : string  := "asym"; -- xil_prim, generic, asym are valid options
893
      device    : string  := "altera"   -- xilinx, altera are valid options
894 63 JonasDC
    );
895
    port(
896
      -- system clock
897
      clk : in std_logic;
898
      -- data interface (plb side)
899
      data_in      : in std_logic_vector(31 downto 0);
900
      data_out     : out std_logic_vector(31 downto 0);
901 75 JonasDC
      rw_address   : in std_logic_vector(8 downto 0);
902 63 JonasDC
      write_enable : in std_logic;
903
      -- operand interface (multiplier side)
904
      op_sel    : in std_logic_vector(log2(nr_op)-1 downto 0);
905
      xy_out    : out std_logic_vector((width-1) downto 0);
906
      m         : out std_logic_vector((width-1) downto 0);
907
      result_in : in std_logic_vector((width-1) downto 0);
908
      -- control signals
909
      load_result    : in std_logic;
910
      result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
911
      collision      : out std_logic;
912
      modulus_sel    : in std_logic_vector(log2(nr_m)-1 downto 0)
913
    );
914 69 JonasDC
  end component operand_mem;
915 63 JonasDC
 
916
 
917 69 JonasDC
 
918 63 JonasDC
  ---------------------------- TOP LEVEL -----------------------------
919
 
920
  --------------------------------------------------------------------
921
  -- mod_sim_exp_core
922
  --------------------------------------------------------------------
923
  --    toplevel of the modular simultaneous exponentiation core
924
  --    contains an operand and modulus ram, multiplier, an exponent fifo
925
  --    and control logic
926
  -- 
927
  component mod_sim_exp_core is
928
    generic(
929 65 JonasDC
      C_NR_BITS_TOTAL   : integer := 1536;
930 63 JonasDC
      C_NR_STAGES_TOTAL : integer := 96;
931 65 JonasDC
      C_NR_STAGES_LOW   : integer := 32;
932
      C_SPLIT_PIPELINE  : boolean := true;
933 69 JonasDC
      C_FIFO_DEPTH      : integer := 32;
934
      C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
935 84 JonasDC
      C_FPGA_MAN        : string  := "xilinx"   -- xilinx, altera are valid options
936 63 JonasDC
    );
937
    port(
938
      clk   : in  std_logic;
939
      reset : in  std_logic;
940
        -- operand memory interface (plb shared memory)
941
      write_enable : in  std_logic; -- write data to operand ram
942
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
943 75 JonasDC
      rw_address   : in  std_logic_vector (8 downto 0); -- operand ram address bus
944 63 JonasDC
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
945
      collision    : out std_logic; -- write collision
946
        -- op_sel fifo interface
947
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
948
      fifo_push   : in  std_logic;  -- push data in exponent fifo
949
      fifo_full   : out std_logic;  -- high if fifo is full
950
      fifo_nopush : out std_logic;  -- high if error during push
951
        -- control signals
952
      start          : in  std_logic; -- start multiplication/exponentiation
953
      exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
954
      ready          : out std_logic; -- calculations done
955 75 JonasDC
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
956
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
957
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
958 63 JonasDC
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
959 65 JonasDC
      calc_time      : out std_logic;
960 75 JonasDC
      modulus_sel    : in std_logic -- selects which modulus to use for multiplications
961 63 JonasDC
    );
962
  end component mod_sim_exp_core;
963 65 JonasDC
 
964 63 JonasDC
 
965 3 JonasDC
end package mod_sim_exp_pkg;

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