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1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 63 JonasDC
library mod_sim_exp;
51
use mod_sim_exp.std_functions.all;
52 9 JonasDC
 
53 3 JonasDC
package mod_sim_exp_pkg is
54 37 JonasDC
  --------------------------------------------------------------------
55
  ---------------------- COMPONENT DECLARATIONS ----------------------
56
  --------------------------------------------------------------------
57
 
58 63 JonasDC
  --------------------------- MULTIPLIER -----------------------------
59
 
60 37 JonasDC
  --------------------------------------------------------------------
61 16 JonasDC
  -- d_flip_flop
62
  --------------------------------------------------------------------
63
  --    1-bit D flip-flop with asynchronous active high reset
64
  -- 
65 9 JonasDC
  component d_flip_flop is
66
    port(
67
      core_clk : in  std_logic; -- clock signal
68
      reset    : in  std_logic; -- active high reset
69
      din      : in  std_logic; -- data in
70
      dout     : out std_logic  -- data out
71 3 JonasDC
    );
72 9 JonasDC
  end component d_flip_flop;
73
 
74 16 JonasDC
  --------------------------------------------------------------------
75
  -- register_1b
76
  --------------------------------------------------------------------
77
  --    1-bit register with asynchronous reset and clock enable
78
  -- 
79 9 JonasDC
  component register_1b is
80
    port(
81
      core_clk : in  std_logic; -- clock input
82
      ce       : in  std_logic; -- clock enable (active high)
83
      reset    : in  std_logic; -- reset (active high)
84
      din      : in  std_logic; -- data in
85
      dout     : out std_logic  -- data out
86 3 JonasDC
    );
87 9 JonasDC
  end component register_1b;
88 3 JonasDC
 
89 16 JonasDC
  --------------------------------------------------------------------
90
  -- register_n
91
  --------------------------------------------------------------------
92
  --    n-bit register with asynchronous reset and clock enable
93
  -- 
94 9 JonasDC
  component register_n is
95
    generic(
96 16 JonasDC
      width : integer := 4
97 3 JonasDC
    );
98 9 JonasDC
    port(
99
      core_clk : in  std_logic; -- clock input
100
      ce       : in  std_logic; -- clock enable (active high)
101
      reset    : in  std_logic; -- reset (active high)
102 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
103
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
104 3 JonasDC
    );
105 9 JonasDC
  end component register_n;
106 3 JonasDC
 
107 16 JonasDC
  --------------------------------------------------------------------
108
  -- cell_1b_adder
109
  --------------------------------------------------------------------
110
  --    1-bit full adder cell using combinatorial logic
111
  --    
112 3 JonasDC
  component cell_1b_adder is
113
    port (
114 9 JonasDC
      -- input operands a, b
115
      a    : in  std_logic;
116
      b    : in  std_logic;
117
      -- carry in, out
118
      cin  : in  std_logic;
119
      cout : out  std_logic;
120
      -- result out
121
      r    : out  std_logic
122 3 JonasDC
    );
123
  end component cell_1b_adder;
124
 
125 16 JonasDC
  --------------------------------------------------------------------
126
  -- cell_1b_mux
127
  --------------------------------------------------------------------
128
  --    1-bit mux for a standard cell in the montgommery multiplier 
129
  --    systolic array
130
  -- 
131 3 JonasDC
  component cell_1b_mux is
132
    port (
133 9 JonasDC
      -- input bits
134
      my     : in  std_logic;
135 3 JonasDC
      y      : in  std_logic;
136
      m      : in  std_logic;
137 9 JonasDC
      -- selection bits
138 3 JonasDC
      x      : in  std_logic;
139
      q      : in  std_logic;
140 9 JonasDC
      -- mux out
141 3 JonasDC
      result : out std_logic
142
    );
143
  end component cell_1b_mux;
144
 
145 16 JonasDC
  --------------------------------------------------------------------
146
  -- cell_1b
147
  --------------------------------------------------------------------
148
  --    1-bit cell for the systolic array
149
  -- 
150 3 JonasDC
  component cell_1b is
151
    port (
152 9 JonasDC
      -- operand input bits (m+y, y and m)
153 3 JonasDC
      my   : in  std_logic;
154
      y    : in  std_logic;
155
      m    : in  std_logic;
156 16 JonasDC
      -- operand x input bit and q
157 3 JonasDC
      x    : in  std_logic;
158
      q    : in  std_logic;
159 9 JonasDC
      -- previous result input bit
160 3 JonasDC
      a    : in  std_logic;
161 9 JonasDC
      -- carry's
162 3 JonasDC
      cin  : in  std_logic;
163
      cout : out std_logic;
164 9 JonasDC
      -- cell result out
165 3 JonasDC
      r    : out std_logic
166
    );
167
  end component cell_1b;
168
 
169 16 JonasDC
  --------------------------------------------------------------------
170
  -- adder_block
171
  --------------------------------------------------------------------
172
  --    (width)-bit full adder block using cell_1b_adders with buffered
173
  --    carry out
174
  -- 
175 9 JonasDC
  component adder_block is
176
    generic (
177
      width : integer := 32 --adder operand widths
178
    );
179
    port (
180
      -- clock input
181
      core_clk : in std_logic;
182
      -- adder input operands a, b (width)-bit
183
      a : in std_logic_vector((width-1) downto 0);
184
      b : in std_logic_vector((width-1) downto 0);
185
      -- carry in, out
186
      cin   : in std_logic;
187
      cout  : out std_logic;
188
      -- adder result out (width)-bit
189
      r : out std_logic_vector((width-1) downto 0)
190
    );
191
  end component adder_block;
192
 
193 16 JonasDC
  --------------------------------------------------------------------
194 17 JonasDC
  -- standard_cell_block
195
  --------------------------------------------------------------------
196
  --    a standard cell block of (width)-bit for the montgommery multiplier 
197
  --    systolic array
198
  -- 
199
  component standard_cell_block is
200
    generic (
201
      width : integer := 16
202
    );
203
    port (
204
      -- modulus and y operand input (width)-bit
205
      my   : in  std_logic_vector((width-1) downto 0);
206
      y    : in  std_logic_vector((width-1) downto 0);
207
      m    : in  std_logic_vector((width-1) downto 0);
208
      -- q and x operand input (serial input)
209
      x    : in  std_logic;
210
      q    : in  std_logic;
211
      -- previous result in (width)-bit
212
      a    : in  std_logic_vector((width-1) downto 0);
213
      -- carry in and out
214
      cin  : in std_logic;
215
      cout : out std_logic;
216
      -- result out (width)-bit
217
      r    : out  std_logic_vector((width-1) downto 0)
218
    );
219
  end component standard_cell_block;
220
 
221
  --------------------------------------------------------------------
222 19 JonasDC
  -- counter_sync
223
  --------------------------------------------------------------------
224
  --    counter with synchronous count enable. It generates an
225
  --    overflow when max_value is reached
226
  -- 
227
  component counter_sync is
228
    generic(
229
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
230
    );
231
    port(
232
      reset_value : in integer;   -- value the counter counts to
233
      core_clk    : in std_logic; -- clock input
234
      ce          : in std_logic; -- count enable
235
      reset       : in std_logic; -- reset input
236
      overflow    : out std_logic -- gets high when counter reaches reset_value
237
    );
238
  end component counter_sync;
239 18 JonasDC
 
240 19 JonasDC
  --------------------------------------------------------------------
241
  -- stepping_logic
242
  --------------------------------------------------------------------
243
  --    stepping logic for the pipeline, generates the start pulses for the
244
  --    first stage and keeps track of when the last stages are done
245
  -- 
246
  component stepping_logic is
247
    generic(
248
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
249
      t : integer := 192    -- total nr of steps in the pipeline
250
    );
251
    port(
252
      core_clk          : in  std_logic;  -- clock input
253
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
254
      reset             : in  std_logic;  -- reset signal
255
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
256
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
257
      start_first_stage : out std_logic;  -- start pulse output for first stage
258
      stepping_done     : out std_logic   -- done signal
259
    );
260
  end component stepping_logic;
261
 
262 20 JonasDC
  --------------------------------------------------------------------
263
  -- x_shift_reg
264
  --------------------------------------------------------------------
265
  --    shift register for the x operand of the multiplier
266
  --    outputs the lsb of the register or bit at offset according to the
267
  --    selected pipeline part 
268
  -- 
269
  component x_shift_reg is
270
    generic(
271
      n  : integer := 1536; -- width of the operands (# bits)
272
      t  : integer := 48;   -- total number of stages
273
      tl : integer := 16    -- lower number of stages
274
    );
275
    port(
276
      -- clock input
277
      clk    : in  std_logic;
278
      -- x operand in (n-bit)
279
      x_in   : in  std_logic_vector((n-1) downto 0);
280
      -- control signals
281
      reset  : in  std_logic; -- reset, clears register
282
      load_x : in  std_logic; -- load operand into shift register   
283
      next_x : in  std_logic; -- next bit of x
284
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
285
      -- x operand bit out (serial)
286 21 JonasDC
      xi     : out std_logic
287 20 JonasDC
    );
288
  end component x_shift_reg;
289 63 JonasDC
 
290 9 JonasDC
  component autorun_cntrl is
291
    port (
292
      clk              : in  std_logic;
293
      reset            : in  std_logic;
294
      start            : in  std_logic;
295
      done             : out  std_logic;
296
      op_sel           : out  std_logic_vector (1 downto 0);
297
      start_multiplier : out  std_logic;
298
      multiplier_done  : in  std_logic;
299
      read_buffer      : out  std_logic;
300
      buffer_din       : in  std_logic_vector (31 downto 0);
301
      buffer_empty     : in  std_logic
302
    );
303
  end component autorun_cntrl;
304
 
305 39 JonasDC
  --------------------------------------------------------------------
306
  -- mont_ctrl
307
  --------------------------------------------------------------------
308
  --    This module controls the montgommery mutliplier and controls traffic between
309
  --    RAM and multiplier. Also contains the autorun logic for exponentiations.
310
  -- 
311 3 JonasDC
  component mont_ctrl is
312
    port (
313
      clk   : in std_logic;
314
      reset : in std_logic;
315
        -- bus side
316
      start           : in std_logic;
317
      x_sel_single    : in std_logic_vector(1 downto 0);
318
      y_sel_single    : in std_logic_vector(1 downto 0);
319
      run_auto        : in std_logic;
320
      op_buffer_empty : in std_logic;
321
      op_sel_buffer   : in std_logic_vector(31 downto 0);
322
      read_buffer     : out std_logic;
323
      done            : out std_logic;
324
      calc_time       : out std_logic;
325
        -- multiplier side
326
      op_sel           : out std_logic_vector(1 downto 0);
327
      load_x           : out std_logic;
328
      load_result      : out std_logic;
329
      start_multiplier : out std_logic;
330
      multiplier_ready : in std_logic
331
    );
332
  end component mont_ctrl;
333
 
334 25 JonasDC
  component sys_stage is
335
    generic(
336
      width : integer := 32 -- width of the stage
337
    );
338
    port(
339
      -- clock input
340
      core_clk : in  std_logic;
341
      -- modulus and y operand input (width)-bit
342
      y        : in  std_logic_vector((width-1) downto 0);
343
      m        : in  std_logic_vector((width) downto 0);
344
      my_cin   : in  std_logic;
345
      my_cout  : out std_logic;
346
      -- q and x operand input (serial input)
347
      xin      : in  std_logic;
348
      qin      : in  std_logic;
349
      -- q and x operand output (serial output)
350
      xout     : out std_logic;
351
      qout     : out std_logic;
352
      -- msb input (lsb from next stage, for shift right operation)
353
      a_msb    : in  std_logic;
354
      a_0      : out std_logic;
355
      -- carry out(clocked) and in
356
      cin      : in  std_logic;
357
      cout     : out std_logic;
358
      -- reduction adder carry's
359
      red_cin  : in std_logic;
360
      red_cout : out std_logic;
361
      -- control singals
362
      start    : in  std_logic;
363
      reset    : in  std_logic;
364
      done     : out std_logic;
365
      -- result out
366
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
367
      r        : out std_logic_vector((width-1) downto 0)
368
    );
369
  end component sys_stage;
370 30 JonasDC
 
371
  --------------------------------------------------------------------
372
  -- sys_last_cell_logic
373
  --------------------------------------------------------------------   
374
  --    logic needed as the last piece in the systolic array pipeline
375
  --    calculates the last 2 bits of the cell_result and finishes the reduction
376
  --    also generates the result selection signal
377
  -- 
378
  component sys_last_cell_logic is
379
    port  (
380
      core_clk : in std_logic;    -- clock input
381
      reset    : in std_logic;
382
      a_0      : out std_logic;   -- a_msb for last stage
383
      cin      : in std_logic;    -- cout from last stage
384
      red_cin  : in std_logic;    -- red_cout from last stage
385
      r_sel    : out std_logic;   -- result selection bit
386
      start    : in std_logic     -- done signal from last stage
387
    );
388
  end component sys_last_cell_logic;
389 25 JonasDC
 
390
  --------------------------------------------------------------------
391 31 JonasDC
  -- sys_first_cell_logic
392
  --------------------------------------------------------------------     
393
  --    logic needed as the first piece in the systolic array pipeline
394
  --    calculates the first my_cout and generates q signal
395
  -- 
396
  component sys_first_cell_logic is
397
    port  (
398
      m0       : in std_logic;    -- lsb from m operand
399
      y0       : in std_logic;    -- lsb from y operand
400
      my_cout  : out std_logic;   -- my_cin for first stage
401
      xi       : in std_logic;    -- xi operand input
402
      xout     : out std_logic;   -- xin for first stage
403
      qout     : out std_logic;   -- qin for first stage
404
      cout     : out std_logic;   -- cin for first stage
405
      a_0      : in std_logic;    -- a_0 from first stage
406
      red_cout : out std_logic    -- red_cin for first stage
407
    );
408
  end component sys_first_cell_logic;
409
 
410
  --------------------------------------------------------------------
411 25 JonasDC
  -- sys_pipeline
412
  -------------------------------------------------------------------- 
413
  --    the pipelined systolic array for a montgommery multiplier
414
  --    contains a structural description of the pipeline using the systolic stages
415
  -- 
416
  component sys_pipeline is
417
    generic(
418
      n  : integer := 1536; -- width of the operands (# bits)
419 37 JonasDC
      t  : integer := 192;  -- total number of stages (minimum 2)
420
      tl : integer := 64;   -- lower number of stages (minimum 1)
421
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
422
                              -- if false there are no lower stages, only t counts
423 25 JonasDC
    );
424
    port(
425
      -- clock input
426
      core_clk : in  std_logic;
427
      -- modulus and y opperand input (n)-bit
428
      y        : in  std_logic_vector((n-1) downto 0);
429
      m        : in  std_logic_vector((n-1) downto 0);
430
      -- x operand input (serial)
431
      xi       : in  std_logic;
432
      next_x   : out std_logic; -- next x operand bit
433
      -- control signals
434
      start    : in  std_logic; -- start multiplier
435
      reset    : in  std_logic;
436
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
437
      -- result out
438
      r        : out std_logic_vector((n-1) downto 0)
439
    );
440
  end component sys_pipeline;
441
 
442
  component mont_multiplier is
443
  generic (
444 37 JonasDC
    n     : integer := 1536;  -- width of the operands
445
    t     : integer := 96;    -- total number of stages (minimum 2)
446
    tl    : integer := 32;    -- lower number of stages (minimum 1)
447
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
448
                              -- if false there are no lower stages, only t counts
449 25 JonasDC
  );
450
  port (
451
    -- clock input
452
    core_clk : in std_logic;
453
    -- operand inputs
454
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
455
    m        : in std_logic_vector((n-1) downto 0); -- modulus
456
    -- result output
457
    r        : out std_logic_vector((n-1) downto 0);  -- result
458
    -- control signals
459
    start    : in std_logic;
460
    reset    : in std_logic;
461
    p_sel    : in std_logic_vector(1 downto 0);
462
    load_x   : in std_logic;
463
    ready    : out std_logic
464
  );
465
  end component mont_multiplier;
466 63 JonasDC
 
467
 
468
  ------------------------------ MEMORY ------------------------------
469 25 JonasDC
 
470 69 JonasDC
  -------------------------- xil_prim specific -----------------------
471 63 JonasDC
  --------------------------------------------------------------------
472
  -- operand_dp
473
  --------------------------------------------------------------------
474
  --    true dual port RAM 512x4, uses xilinx primitives
475
  --
476
  component operand_dp is
477
    port (
478
      clka  : in std_logic;
479
      wea   : in std_logic_vector(0 downto 0);
480
      addra : in std_logic_vector(5 downto 0);
481
      dina  : in std_logic_vector(31 downto 0);
482 94 JonasDC
      douta : out std_logic_vector(31 downto 0);
483 63 JonasDC
      clkb  : in std_logic;
484
      web   : in std_logic_vector(0 downto 0);
485 94 JonasDC
      addrb : in std_logic_vector(1 downto 0);
486 63 JonasDC
      dinb  : in std_logic_vector(511 downto 0);
487 94 JonasDC
      doutb : out std_logic_vector(511 downto 0)
488 63 JonasDC
    );
489
  end component operand_dp;
490
 
491
  --------------------------------------------------------------------
492
  -- operand_sp
493
  --------------------------------------------------------------------
494
  --    dual port RAM 512x2, uses xilinx primitives
495
  --
496
  component operands_sp is
497
    port (
498
      clka  : in std_logic;
499
      wea   : in std_logic_vector(0 downto 0);
500
      addra : in std_logic_vector(4 downto 0);
501
      dina  : in std_logic_vector(31 downto 0);
502
      douta : out std_logic_vector(511 downto 0)
503
    );
504
  end component operands_sp;
505
 
506
  --------------------------------------------------------------------
507 69 JonasDC
  -- fifo_primitive
508
  --------------------------------------------------------------------
509
  --    a xilinx fifo primitive wrapper
510
  -- 
511
  component fifo_primitive is
512
    port (
513 94 JonasDC
      pop_clk  : in  std_logic;
514
      push_clk : in  std_logic;
515
      din      : in  std_logic_vector (31 downto 0);
516
      dout     : out  std_logic_vector (31 downto 0);
517
      empty    : out  std_logic;
518
      full     : out  std_logic;
519
      push     : in  std_logic;
520
      pop      : in  std_logic;
521
      reset    : in std_logic;
522
      nopop    : out std_logic;
523
      nopush   : out std_logic
524 69 JonasDC
    );
525
  end component fifo_primitive;
526
 
527
  --------------------------------------------------------------------
528
  -- operand_ram
529
  --------------------------------------------------------------------
530
  --    RAM for the operands, fixed width of 1536-bit and depth of 4
531
  --    uses xilinx primitives
532
  --
533
  component operand_ram is
534
    port(
535
      -- global ports
536
      collision : out std_logic;
537
      -- bus side connections (32-bit serial)
538 94 JonasDC
      bus_clk       : in std_logic;
539 69 JonasDC
      operand_addr   : in std_logic_vector(5 downto 0);
540
      operand_in     : in std_logic_vector(31 downto 0);
541
      operand_in_sel : in std_logic_vector(1 downto 0);
542
      result_out     : out std_logic_vector(31 downto 0);
543
      write_operand  : in std_logic;
544
      -- multiplier side connections (1536 bit parallel)
545 94 JonasDC
      core_clk       : in std_logic;
546 69 JonasDC
      result_dest_op  : in std_logic_vector(1 downto 0);
547
      operand_out     : out std_logic_vector(1535 downto 0);
548
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
549
      write_result    : in std_logic;
550
      result_in       : in std_logic_vector(1535 downto 0)
551
    );
552
  end component operand_ram;
553
 
554
  --------------------------------------------------------------------
555
  -- modulus_ram
556
  --------------------------------------------------------------------
557
  --    RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives
558
  --
559
  component modulus_ram is
560
    port(
561
      clk           : in std_logic;
562
      modulus_addr  : in std_logic_vector(5 downto 0);
563
      write_modulus : in std_logic;
564
      modulus_in    : in std_logic_vector(31 downto 0);
565
      modulus_out   : out std_logic_vector(1535 downto 0)
566
    );
567
  end component modulus_ram;
568
 
569
 
570
  ------------------------- generic modules --------------------------
571
 
572
  --------------------------------------------------------------------
573 63 JonasDC
  -- dpram_generic
574
  --------------------------------------------------------------------
575
  --    behavorial description of a dual port ram with one 32-bit
576
  --    write port and one 32-bit read port
577
  -- 
578
  component dpram_generic is
579
    generic (
580
      depth : integer := 2
581
    );
582
    port  (
583 94 JonasDC
      -- write port A
584
      clkA   : in std_logic;
585
      waddrA : in std_logic_vector(log2(depth)-1 downto 0);
586
      weA    : in std_logic;
587
      dinA   : in std_logic_vector(31 downto 0);
588
      -- read port B
589
      clkB   : in std_logic;
590
      raddrB : in std_logic_vector(log2(depth)-1 downto 0);
591
      doutB  : out std_logic_vector(31 downto 0)
592 63 JonasDC
    );
593
  end component dpram_generic;
594
 
595
  --------------------------------------------------------------------
596
  -- tdpram_generic
597
  --------------------------------------------------------------------
598
  --    behavorial description of a true dual port ram with 2
599
  --    32-bit write/read ports
600
  -- 
601
  component tdpram_generic is
602
    generic (
603
      depth : integer := 9
604
    );
605
    port (
606
      -- port A
607
      clkA  : in std_logic;
608
      addrA : in std_logic_vector(log2(depth)-1 downto 0);
609
      weA   : in std_logic;
610
      dinA  : in std_logic_vector(31 downto 0);
611
      doutA : out std_logic_vector(31 downto 0);
612
      -- port B
613
      clkB  : in std_logic;
614
      addrB : in std_logic_vector(log2(depth)-1 downto 0);
615
      weB   : in std_logic;
616
      dinB  : in std_logic_vector(31 downto 0);
617
      doutB : out std_logic_vector(31 downto 0)
618
    );
619
  end component tdpram_generic;
620
 
621
  --------------------------------------------------------------------
622
  -- fifo_generic
623
  --------------------------------------------------------------------
624
  --    a behavorial implementation of a fifo that is designed to 
625
  --    infer blockram
626
  -- 
627
  component fifo_generic is
628
    generic (
629
      depth : integer := 32
630
    );
631
    port  (
632
      clk    : in  std_logic; -- clock input
633
      din    : in  std_logic_vector (31 downto 0); -- 32 bit input data for push
634
      dout   : out  std_logic_vector (31 downto 0); -- 32 bit output data for pop
635
      empty  : out  std_logic; -- empty flag, 1 when FIFO is empty
636
      full   : out  std_logic; -- full flag, 1 when FIFO is full
637
      push   : in  std_logic;
638
      pop    : in  std_logic;
639
      reset  : in std_logic;
640
      nopop  : out std_logic;
641
      nopush : out std_logic
642
    );
643
  end component fifo_generic;
644
 
645
  --------------------------------------------------------------------
646
  -- modulus_ram_gen
647
  --------------------------------------------------------------------
648 69 JonasDC
  --    structural description of a RAM to hold the modulus, with 
649 63 JonasDC
  --    adjustable width and depth(nr of moduluses)
650
  --
651
  component modulus_ram_gen is
652
    generic(
653
      width : integer := 1536;  -- must be a multiple of 32
654
      depth : integer := 2      -- nr of moduluses
655
    );
656
    port(
657
        -- bus side
658 94 JonasDC
      bus_clk        : in std_logic;
659 63 JonasDC
      write_modulus  : in std_logic; -- write enable
660
      modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
661
      modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
662
      modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
663
      modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
664
        -- multiplier side
665 94 JonasDC
      core_clk       : in std_logic;
666 63 JonasDC
      modulus_out    : out std_logic_vector(width-1 downto 0)
667
    );
668
  end component modulus_ram_gen;
669
 
670
  --------------------------------------------------------------------
671
  -- operand_ram_gen
672
  --------------------------------------------------------------------
673
  --    behavorial description of a RAM to hold the operands, with 
674
  --    adjustable width and depth(nr of operands)
675
  --
676
  component operand_ram_gen is
677
    generic(
678
      width : integer := 1536; -- width of the operands
679
      depth : integer := 4     -- nr of operands
680
    );
681
    port(
682
        -- global ports
683
      collision : out std_logic; -- 1 if simultaneous write on RAM
684
        -- bus side connections (32-bit serial)
685 94 JonasDC
      bus_clk        : in std_logic;
686 63 JonasDC
      write_operand  : in std_logic; -- write_enable
687
      operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
688
      operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
689
      operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
690
      result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
691
      operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
692
        -- multiplier side connections (width-bit parallel)
693 94 JonasDC
      core_clk        : in std_logic;
694 63 JonasDC
      result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
695
      operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
696
      write_result    : in std_logic; -- write enable for multiplier side
697
      result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
698
    );
699
  end component operand_ram_gen;
700
 
701 69 JonasDC
 
702
 
703
  ------------------------ asymmetric modules ------------------------
704
 
705 63 JonasDC
  --------------------------------------------------------------------
706 69 JonasDC
  -- dpram_asym
707 63 JonasDC
  --------------------------------------------------------------------
708 69 JonasDC
  --    behavorial description of an asymmetric dual port ram
709
  --    with one (wrwidth)-bit write port and one 32-bit read
710
  --    port. Made using the templates of xilinx and altera for
711
  --    asymmetric ram.
712 63 JonasDC
  --
713 69 JonasDC
  component dpram_asym is
714 94 JonasDC
    generic (
715 69 JonasDC
      rddepth : integer := 4; -- nr of 32-bit words
716
      wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
717
      device  : string  := "xilinx"  -- device template to use
718 63 JonasDC
    );
719 94 JonasDC
    port (
720 69 JonasDC
      -- write port
721 94 JonasDC
      clkA   : in std_logic;
722
      waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
723
      weA    : in std_logic;
724
      dinA   : in std_logic_vector(wrwidth-1 downto 0);
725 69 JonasDC
      -- read port
726 94 JonasDC
      clkB   : in std_logic;
727
      raddrB : in std_logic_vector(log2(rddepth)-1 downto 0);
728
      doutB  : out std_logic_vector(31 downto 0)
729 69 JonasDC
    );
730
  end component dpram_asym;
731 63 JonasDC
 
732 69 JonasDC
  --------------------------------------------------------------------
733
  -- dpramblock_asym
734
  --------------------------------------------------------------------
735
  --    structural description of an asymmetric dual port ram
736
  --    with one 32-bit write port and one (width)-bit read
737
  --    port.
738
  -- 
739
  component dpramblock_asym is
740 94 JonasDC
    generic (
741 69 JonasDC
      width  : integer := 256;  -- read width
742
      depth  : integer := 2;    -- nr of (width)-bit words
743
      device : string  := "xilinx"
744
    );
745 94 JonasDC
    port (
746
      -- write port A
747
      clkA   : in std_logic;
748
      waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
749
      weA    : in std_logic;
750
      dinA   : in std_logic_vector(31 downto 0);
751
      -- read port B
752
      clkB   : in std_logic;
753
      raddrB : in std_logic_vector(log2(depth)-1 downto 0);
754
      doutB  : out std_logic_vector(width-1 downto 0)
755 69 JonasDC
    );
756
  end component dpramblock_asym;
757 63 JonasDC
 
758 69 JonasDC
  --------------------------------------------------------------------
759
  -- tdpram_asym
760
  --------------------------------------------------------------------
761
  --    behavorial description of an asymmetric true dual port
762
  --    ram with one (widthA)-bit read/write port and one 32-bit
763
  --    read/write port. Made using the templates of xilinx and
764
  --    altera for asymmetric ram.
765
  --
766
  component tdpram_asym is
767 94 JonasDC
    generic (
768 69 JonasDC
      depthB : integer := 4; -- nr of 32-bit words
769
      widthA : integer := 2;  -- port A width, must be smaller than or equal to 32
770
      device : string  := "xilinx"
771 63 JonasDC
    );
772 94 JonasDC
    port  (
773 69 JonasDC
      -- port A (widthA)-bit
774 94 JonasDC
      clkA  : in std_logic;
775 69 JonasDC
      addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
776
      weA   : in std_logic;
777
      dinA  : in std_logic_vector(widthA-1 downto 0);
778
      doutA : out std_logic_vector(widthA-1 downto 0);
779
      -- port B 32-bit
780 94 JonasDC
      clkB  : in std_logic;
781 69 JonasDC
      addrB : in std_logic_vector(log2(depthB)-1 downto 0);
782
      weB   : in std_logic;
783
      dinB  : in std_logic_vector(31 downto 0);
784
      doutB : out std_logic_vector(31 downto 0)
785
    );
786
  end component tdpram_asym;
787 63 JonasDC
 
788 69 JonasDC
  --------------------------------------------------------------------
789
  -- tdpramblock_asym
790
  --------------------------------------------------------------------
791
  --    structural description of an asymmetric true dual port
792
  --    ram with one 32-bit read/write port and one (width)-bit
793
  --    read/write port.
794
  --
795
  component tdpramblock_asym is
796
    generic (
797
      depth  : integer := 4;    -- nr of (width)-bit words
798
      width  : integer := 512;  -- width of portB
799
      device : string  := "xilinx"
800 63 JonasDC
    );
801 94 JonasDC
    port (
802 69 JonasDC
      -- port A 32-bit
803 94 JonasDC
      clkA  : in std_logic;
804 69 JonasDC
      addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
805
      weA   : in std_logic;
806
      dinA  : in std_logic_vector(31 downto 0);
807
      doutA : out std_logic_vector(31 downto 0);
808
      -- port B (width)-bit
809 94 JonasDC
      clkB  : in std_logic;
810 69 JonasDC
      addrB : in std_logic_vector(log2(depth)-1 downto 0);
811
      weB   : in std_logic;
812
      dinB  : in std_logic_vector(width-1 downto 0);
813
      doutB : out std_logic_vector(width-1 downto 0)
814
    );
815
  end component tdpramblock_asym;
816 63 JonasDC
 
817
  --------------------------------------------------------------------
818 69 JonasDC
  -- modulus_ram_asym
819 63 JonasDC
  --------------------------------------------------------------------
820 69 JonasDC
  --    BRAM memory and logic to store the modulus, due to the
821
  --    achitecture, a minimum depth of 2 is needed for this
822
  --    module to be inferred into blockram, this version is
823
  --    slightly more performant than modulus_ram_gen and uses
824
  --    less resources. but does not work on every fpga, only
825
  --    the ones that support asymmetric rams.
826 63 JonasDC
  --
827 69 JonasDC
  component modulus_ram_asym is
828
    generic(
829
      width : integer := 1536;  -- must be a multiple of 32
830
      depth : integer := 2;     -- nr of moduluses
831
      device : string := "xilinx"
832
    );
833
    port(
834
        -- bus side
835 94 JonasDC
      bus_clk        : in std_logic;
836 69 JonasDC
      write_modulus  : in std_logic; -- write enable
837
      modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
838
      modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
839
      modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
840
      modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
841
        -- multiplier side
842 94 JonasDC
      core_clk       : in std_logic;
843 69 JonasDC
      modulus_out    : out std_logic_vector(width-1 downto 0)
844
    );
845
  end component modulus_ram_asym;
846
 
847
  --------------------------------------------------------------------
848
  -- operand_ram_asym
849
  --------------------------------------------------------------------
850
  --    BRAM memory and logic to store the operands, due to the
851
  --    achitecture, a minimum depth of 2 is needed for this
852
  --    module to be inferred into blockram, this version is
853
  --    slightly more performant than operand_ram_gen and uses
854
  --    less resources. but does not work on every fpga, only
855
  --    the ones that support asymmetric rams. 
856
  --
857
  component operand_ram_asym is
858
    generic(
859
      width  : integer := 1536; -- width of the operands
860
      depth  : integer := 4;    -- nr of operands
861
      device : string  := "xilinx"
862
    );
863
    port(
864
        -- global ports
865
      collision : out std_logic; -- 1 if simultaneous write on RAM
866
        -- bus side connections (32-bit serial)
867 94 JonasDC
      bus_clk        : in std_logic;
868 69 JonasDC
      write_operand  : in std_logic; -- write_enable
869
      operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
870
      operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
871
      operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
872
      result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
873
      operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
874
        -- multiplier side connections (width-bit parallel)
875 94 JonasDC
      core_clk        : in std_logic;
876 69 JonasDC
      result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
877
      operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
878
      write_result    : in std_logic; -- write enable for multiplier side
879
      result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
880
    );
881
  end component operand_ram_asym;
882
 
883
  --------------------------------------------------------------------
884
  -- operand_mem
885
  --------------------------------------------------------------------
886
  --    RAM memory and logic to the store operands and the
887
  --    modulus for the montgomery multiplier, the user has a
888
  --    choise between 3 memory styles, more detail in the
889
  --    documentation.
890
  --
891 63 JonasDC
  --    address structure:
892
  --    bit: highest   ->  '1': modulus
893
  --                       '0': operands
894
  --    bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
895 69 JonasDC
  --                                        modulus_in_sel in case of highest bit = '1'
896 63 JonasDC
  --    bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
897
  -- 
898 69 JonasDC
  component operand_mem is
899 63 JonasDC
    generic(
900 69 JonasDC
      width     : integer := 1536; -- width of the operands
901
      nr_op     : integer := 4; -- nr of operand storages, has to be greater than nr_m
902
      nr_m      : integer := 2; -- nr of modulus storages
903
      mem_style : string  := "asym"; -- xil_prim, generic, asym are valid options
904
      device    : string  := "altera"   -- xilinx, altera are valid options
905 63 JonasDC
    );
906
    port(
907
      -- data interface (plb side)
908 94 JonasDC
      bus_clk      : in std_logic;
909 63 JonasDC
      data_in      : in std_logic_vector(31 downto 0);
910
      data_out     : out std_logic_vector(31 downto 0);
911 75 JonasDC
      rw_address   : in std_logic_vector(8 downto 0);
912 63 JonasDC
      write_enable : in std_logic;
913
      -- operand interface (multiplier side)
914 94 JonasDC
      core_clk  : in std_logic;
915 63 JonasDC
      op_sel    : in std_logic_vector(log2(nr_op)-1 downto 0);
916
      xy_out    : out std_logic_vector((width-1) downto 0);
917
      m         : out std_logic_vector((width-1) downto 0);
918
      result_in : in std_logic_vector((width-1) downto 0);
919
      -- control signals
920
      load_result    : in std_logic;
921
      result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
922
      collision      : out std_logic;
923
      modulus_sel    : in std_logic_vector(log2(nr_m)-1 downto 0)
924
    );
925 69 JonasDC
  end component operand_mem;
926 63 JonasDC
 
927
 
928 94 JonasDC
  ---------------------- CLOCK DOMAIN CROSSING  ----------------------
929 69 JonasDC
 
930 94 JonasDC
  --------------------------------------------------------------------
931
  -- pulse_cdc
932
  --------------------------------------------------------------------
933
  --    transfers a pulse (1clk wide) from clock domain A to clock domain B
934
  --    by using a toggling signal. This design avoids metastable states
935
  -- 
936
  component pulse_cdc is
937
    port (
938
      reset  : in std_logic;
939
      clkA   : in std_logic;
940
      pulseA : in std_logic;
941
      clkB   : in std_logic;
942
      pulseB : out std_logic
943
    );
944
  end component pulse_cdc;
945
 
946
  --------------------------------------------------------------------
947
  -- clk_sync
948
  --------------------------------------------------------------------
949
  --    transfers a signal from clock domain A to clock domain B. 
950
  --    This design avoids metastable states
951
  -- 
952
  component clk_sync is
953
    port (
954
      sigA : in std_logic;
955
      clkB : in std_logic;
956
      sigB : out std_logic
957
    );
958
  end component clk_sync;
959
 
960
 
961 63 JonasDC
  ---------------------------- TOP LEVEL -----------------------------
962
 
963
  --------------------------------------------------------------------
964
  -- mod_sim_exp_core
965
  --------------------------------------------------------------------
966
  --    toplevel of the modular simultaneous exponentiation core
967
  --    contains an operand and modulus ram, multiplier, an exponent fifo
968
  --    and control logic
969
  -- 
970
  component mod_sim_exp_core is
971
    generic(
972 65 JonasDC
      C_NR_BITS_TOTAL   : integer := 1536;
973 63 JonasDC
      C_NR_STAGES_TOTAL : integer := 96;
974 65 JonasDC
      C_NR_STAGES_LOW   : integer := 32;
975
      C_SPLIT_PIPELINE  : boolean := true;
976 94 JonasDC
      C_FIFO_AW         : integer := 7;      -- Address width for FIFO pointers
977
      C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
978 84 JonasDC
      C_FPGA_MAN        : string  := "xilinx"   -- xilinx, altera are valid options
979 63 JonasDC
    );
980
    port(
981 94 JonasDC
      core_clk : in  std_logic;
982
      reset    : in  std_logic;
983 63 JonasDC
        -- operand memory interface (plb shared memory)
984 94 JonasDC
      bus_clk      : in  std_logic;
985 63 JonasDC
      write_enable : in  std_logic; -- write data to operand ram
986
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
987 75 JonasDC
      rw_address   : in  std_logic_vector (8 downto 0); -- operand ram address bus
988 63 JonasDC
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
989
      collision    : out std_logic; -- write collision
990
        -- op_sel fifo interface
991
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
992
      fifo_push   : in  std_logic;  -- push data in exponent fifo
993
      fifo_full   : out std_logic;  -- high if fifo is full
994
      fifo_nopush : out std_logic;  -- high if error during push
995
        -- control signals
996
      start          : in  std_logic; -- start multiplication/exponentiation
997
      exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
998
      ready          : out std_logic; -- calculations done
999 75 JonasDC
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
1000
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
1001
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
1002 63 JonasDC
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
1003 65 JonasDC
      calc_time      : out std_logic;
1004 94 JonasDC
      modulus_sel    : in  std_logic   -- selects which modulus to use for multiplications
1005 63 JonasDC
    );
1006
  end component mod_sim_exp_core;
1007 65 JonasDC
 
1008 63 JonasDC
 
1009 3 JonasDC
end package mod_sim_exp_pkg;

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