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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mont_ctrl.vhd] - Blame information for rev 24

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1 3 JonasDC
----------------------------------------------------------------------  
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----  mont_ctrl                                                   ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    control unit for a pipelined montgomery multiplier, with  ----
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----    split pipeline operation and "auto-run" support           ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - autorun_cntrl                                           ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
45 2 JonasDC
 
46 3 JonasDC
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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51 3 JonasDC
library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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55 24 JonasDC
-- This module controls the montgommery mutliplier and controls traffic between
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-- RAM and multiplier. Also contains the autorun logic for exponentiations.
57 2 JonasDC
entity mont_ctrl is
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  port (
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    clk   : in std_logic;
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    reset : in std_logic;
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      -- bus side
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    start           : in std_logic;
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    x_sel_single    : in std_logic_vector(1 downto 0);
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    y_sel_single    : in std_logic_vector(1 downto 0);
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    run_auto        : in std_logic;
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    op_buffer_empty : in std_logic;
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    op_sel_buffer   : in std_logic_vector(31 downto 0);
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    read_buffer     : out std_logic;
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    buffer_noread   : in std_logic;
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    done            : out std_logic;
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    calc_time       : out std_logic;
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      -- multiplier side
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    op_sel           : out std_logic_vector(1 downto 0);
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    load_x           : out std_logic;
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    load_result      : out std_logic;
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    start_multiplier : out std_logic;
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    multiplier_ready : in std_logic
78 2 JonasDC
  );
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end mont_ctrl;
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81 3 JonasDC
 
82 2 JonasDC
architecture Behavioral of mont_ctrl is
83 24 JonasDC
  signal start_d      : std_logic; -- delayed version of start input
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  signal start_pulse        : std_logic;
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  signal auto_start_pulse   : std_logic;
86 3 JonasDC
  signal start_multiplier_i   : std_logic;
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  signal start_up_counter   : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
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  signal calc_time_i : std_logic; -- high ('1') during multiplication
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  signal x_sel        : std_logic_vector(1 downto 0); -- the operand used as x input
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  signal y_sel        : std_logic_vector(1 downto 0); -- the operand used as y input
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  signal x_sel_buffer : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
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95 24 JonasDC
  signal auto_done             : std_logic;
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  signal start_auto            : std_logic;
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  signal auto_multiplier_done_i : std_logic;
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begin
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        -----------------------------------------------------------------------------------
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        -- Processes related to starting and stopping the multiplier
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        -----------------------------------------------------------------------------------
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        -- generate a start pulse (duration 1 clock cycle) based on ext. start sig
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        START_PULSE_PROC: process(clk)
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        begin
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                if rising_edge(clk) then
108 24 JonasDC
                        start_d <= start;
109 2 JonasDC
                end if;
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        end process START_PULSE_PROC;
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        start_pulse <= start and (not start_d);
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        start_auto <= start_pulse and run_auto;
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        -- to start the multiplier we first need to select the x_operand and
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        -- clock it in the x shift register
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        -- the we select the y_operand and start the multiplier
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        -- start_up_counter
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        --   default state : "100"
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        --   at start pulse counter resets to 0 and counts up to "100"
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        START_MULT_PROC: process(clk, reset)
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        begin
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                if reset = '1' then
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                        start_up_counter <= "100";
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                elsif rising_edge(clk) then
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                        if start_pulse = '1' or auto_start_pulse = '1' then
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                                start_up_counter <= "000";
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                        elsif start_up_counter(2) /= '1' then
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                                start_up_counter <= start_up_counter + '1';
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                        else
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                                start_up_counter <= "100";
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                        end if;
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                else
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                        start_up_counter <= start_up_counter;
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                end if;
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        end process;
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        -- select operands (autorun/single run)
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        x_sel <= x_sel_buffer when (run_auto = '1') else x_sel_single;
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        y_sel <= "11" when (run_auto = '1') else y_sel_single; -- y is operand3 in auto mode
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        -- clock operands to operand_mem output (first x, then y)
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        with start_up_counter(2 downto 1) select
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                op_sel <= x_sel when "00",  -- start_up_counter="00x" (first 2 cycles)
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                          y_sel when others;  -- 
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        load_x <= start_up_counter(0) and (not start_up_counter(1)); -- latch x operand if start_up_counter="x01"
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        -- start multiplier when start_up_counter="x11"
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        start_multiplier_i <= start_up_counter(1) and start_up_counter(0);
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        start_multiplier <= start_multiplier_i;
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        -- signal calc time is high during multiplication
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        CALC_TIME_PROC: process(clk, reset)
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        begin
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                if reset = '1' then
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                        calc_time_i <= '0';
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                elsif rising_edge(clk) then
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                        if start_multiplier_i = '1' then
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                                calc_time_i <= '1';
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                        elsif multiplier_ready = '1' then
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                                calc_time_i <= '0';
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                        else
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                                calc_time_i <= calc_time_i;
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                        end if;
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                else
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                        calc_time_i <= calc_time_i;
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                end if;
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        end process CALC_TIME_PROC;
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        calc_time <= calc_time_i;
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        -- what happens when a multiplication has finished
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        load_result <= multiplier_ready;
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        -- ignore multiplier_ready when in automode, the logic will assert auto_done when finished
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        done <= ((not run_auto) and multiplier_ready) or auto_done;
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176
        -----------------------------------------------------------------------------------
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        -- Processes related to op_buffer cntrl and auto_run mode
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        -- start_auto     -> start autorun mode operation
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        -- auto_start_pulse <- autorun logic starts the multiplier
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        -- auto_done        <- autorun logic signals when autorun operation has finished
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        -- x_sel_buffer   <- autorun logic determines which operand is used as x
182 2 JonasDC
 
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        -- check buffer empty signal
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        -----------------------------------------------------------------------------------
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        -- multiplier_ready is only passed to autorun control when in autorun mode
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        auto_multiplier_done_i <= (multiplier_ready and run_auto);
188 3 JonasDC
 
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  autorun_control_logic : autorun_cntrl port map(
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    clk              => clk,
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    reset            => reset,
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    start            => start_auto,
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    done             => auto_done,
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    op_sel           => x_sel_buffer,
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    start_multiplier => auto_start_pulse,
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    multiplier_done  => auto_multiplier_done_i,
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    read_buffer      => read_buffer,
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    buffer_din       => op_sel_buffer,
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    buffer_empty     => op_buffer_empty
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  );
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end Behavioral;

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