OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mont_multiplier.vhd] - Blame information for rev 37

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 JonasDC
----------------------------------------------------------------------  
2
----  mont_multiplier                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    n-bit montgomery multiplier with a pipelined systolic     ----
10
----    array                                                     ----
11
----                                                              ----
12
----  Dependencies:                                               ----
13
----    - x_shift_reg                                             ----
14
----    - adder_n                                                 ----
15
----    - d_flip_flop                                             ----
16
----    - sys_pipeline                                            ----
17
----    - cell_1b_adder                                           ----
18
----                                                              ----
19
----  Authors:                                                    ----
20
----      - Geoffrey Ottoy, DraMCo research group                 ----
21
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
22
----                                                              ---- 
23
---------------------------------------------------------------------- 
24
----                                                              ---- 
25
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
26
----                                                              ---- 
27
---- This source file may be used and distributed without         ---- 
28
---- restriction provided that this copyright statement is not    ---- 
29
---- removed from the file and that any derivative work contains  ---- 
30
---- the original copyright notice and the associated disclaimer. ---- 
31
----                                                              ---- 
32
---- This source file is free software; you can redistribute it   ---- 
33
---- and/or modify it under the terms of the GNU Lesser General   ---- 
34
---- Public License as published by the Free Software Foundation; ---- 
35
---- either version 2.1 of the License, or (at your option) any   ---- 
36
---- later version.                                               ---- 
37
----                                                              ---- 
38
---- This source is distributed in the hope that it will be       ---- 
39
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
40
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
41
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
42
---- details.                                                     ---- 
43
----                                                              ---- 
44
---- You should have received a copy of the GNU Lesser General    ---- 
45
---- Public License along with this source; if not, download it   ---- 
46
---- from http://www.opencores.org/lgpl.shtml                     ---- 
47
----                                                              ---- 
48
----------------------------------------------------------------------
49
library ieee;
50
use ieee.std_logic_1164.all;
51
use ieee.std_logic_unsigned.all;
52
 
53
library mod_sim_exp;
54
use mod_sim_exp.mod_sim_exp_pkg.all;
55
 
56
-- Structural description of the montgommery multiply pipeline
57
-- contains the x operand shift register, my adder, the pipeline and 
58
-- reduction adder. To do a multiplication, the following actions must take place:
59
-- 
60
--    * load in the x operand in the shift register using the xy bus and load_x
61
--    * place the y operand on the xy bus for the rest of the operation
62
--    * generate a start pulse of 1 clk cycle long on start
63
--    * wait for ready signal
64
--    * result is avaiable on the r bus
65
-- 
66
entity mont_multiplier is
67
  generic (
68 37 JonasDC
    n     : integer := 1536;  -- width of the operands
69
    t     : integer := 96;    -- total number of stages (minimum 2)
70
    tl    : integer := 32;    -- lower number of stages (minimum 1)
71
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
72
                              -- if false there are no lower stages, only t counts
73 25 JonasDC
  );
74
  port (
75
    -- clock input
76
    core_clk : in std_logic;
77
    -- operand inputs
78
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
79
    m        : in std_logic_vector((n-1) downto 0); -- modulus
80
    -- result output
81
    r        : out std_logic_vector((n-1) downto 0);  -- result
82
    -- control signals
83
    start    : in std_logic;
84
    reset    : in std_logic;
85
    p_sel    : in std_logic_vector(1 downto 0);
86
    load_x   : in std_logic;
87
    ready    : out std_logic
88
  );
89
end mont_multiplier;
90
 
91
architecture Structural of mont_multiplier is
92 37 JonasDC
  constant s  : integer := n/t;   -- stage width (# bits)
93 32 JonasDC
  constant nl : integer := s*tl;  -- lower pipeline width (# bits)
94
  constant nh : integer :=  n - nl; -- higher pipeline width (# bits)
95 25 JonasDC
 
96
  signal reset_multiplier : std_logic;
97
  signal start_multiplier : std_logic;
98
 
99 37 JonasDC
  signal p_sel_i : std_logic_vector(1 downto 0);
100 32 JonasDC
  signal t_sel  : integer range 0 to t;  -- width in stages of selected pipeline part
101
  signal n_sel  : integer range 0 to n;  -- width in bits of selected pipeline part
102
 
103 25 JonasDC
  signal next_xi : std_logic;
104
  signal xi : std_logic;
105
 
106
  signal start_first_stage : std_logic;
107
 
108
begin
109 37 JonasDC
 
110 25 JonasDC
  -- multiplier is reset every calculation or reset
111
  reset_multiplier <= reset or start;
112
 
113
  -- start is delayed 1 cycle
114
  delay_1_cycle : d_flip_flop
115
  port map(
116
    core_clk => core_clk,
117
    reset    => reset,
118
    din      => start,
119
    dout     => start_multiplier
120
  );
121
 
122
  -- register to store the x value in 
123
  -- outputs the operand in serial using a shift register 
124
  x_selection : x_shift_reg
125
  generic map(
126
    n  => n,
127 37 JonasDC
    t  => t,
128
    tl => tl
129 25 JonasDC
  )
130
  port map(
131
    clk    => core_clk,
132
    reset  => reset,
133
    x_in   => xy,
134
    load_x => load_x,
135
    next_x => next_xi,
136 37 JonasDC
    p_sel  => p_sel_i,
137 25 JonasDC
    xi     => xi
138
  );
139
 
140 37 JonasDC
----------------------------------------
141
-- SINGLE PIPELINE ASSIGNMENTS
142
----------------------------------------
143
single_pipeline : if split=false generate
144
  p_sel_i <= "11";
145
  t_sel <= t;
146
  n_sel <= n-1;
147
end generate;
148
 
149
----------------------------------------
150
-- SPLIT PIPELINE ASSIGNMENTS
151
----------------------------------------
152
split_pipeline : if split=true generate
153 32 JonasDC
  -- this module controls the pipeline operation
154
  --   width in stages for selected pipeline
155
  with p_sel select
156
    t_sel <=    tl when "01",   -- lower pipeline part
157
              t-tl when "10",   -- higher pipeline part
158
                 t when others; -- full pipeline
159
 
160
  --   width in bits for selected pipeline
161
  with p_sel select
162
    n_sel <= nl-1 when "01",  -- lower pipeline part
163
             nh-1 when "10",  -- higher pipeline part
164
             n-1 when others; -- full pipeline
165
 
166 37 JonasDC
  p_sel_i <= p_sel;
167
end generate;
168
 
169 25 JonasDC
  -- stepping control logic to keep track off the multiplication and when it is done
170
  stepping_control : stepping_logic
171
  generic map(
172
    n => n, -- max nr of steps required to complete a multiplication
173 37 JonasDC
    t => t -- total nr of steps in the pipeline
174 25 JonasDC
  )
175
  port map(
176
    core_clk          => core_clk,
177
    start             => start_multiplier,
178
    reset             => reset_multiplier,
179 32 JonasDC
    t_sel             => t_sel,
180
    n_sel             => n_sel,
181 25 JonasDC
    start_first_stage => start_first_stage,
182
    stepping_done     => ready
183
  );
184
 
185
  systolic_array : sys_pipeline
186
  generic map(
187
    n  => n,
188 37 JonasDC
    t  => t,
189
    tl => tl,
190
    split => split
191 25 JonasDC
  )
192
  port map(
193
    core_clk => core_clk,
194
    y       => xy,
195
    m       => m,
196
    xi      => xi,
197
    next_x  => next_xi,
198
    start   => start_first_stage,
199
    reset   => reset_multiplier,
200 37 JonasDC
    p_sel   => p_sel_i,
201 25 JonasDC
    r       => r
202
  );
203
 
204
end Structural;

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.