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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_gen.vhd] - Blame information for rev 94

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1 63 JonasDC
----------------------------------------------------------------------  
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----  operand_ram_gen                                             ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    BRAM memory and logic to the store the operands           ----
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----    for the montgomery multiplier                             ----            
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----                                                              ---- 
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----  Dependencies:                                               ----
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----    - tdpram_generic                                          ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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-- behavorial description of a RAM to hold the operands, with 
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-- adjustable width and depth(nr of operands)
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entity operand_ram_gen is
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  generic(
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    width : integer := 1536; -- width of the operands
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    depth : integer := 4     -- nr of operands
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  );
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  port(
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      -- global ports
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    collision : out std_logic; -- 1 if simultaneous write on RAM
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      -- bus side connections (32-bit serial)
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    bus_clk        : in std_logic;
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    write_operand  : in std_logic; -- write_enable
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    operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
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    operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
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    operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
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    result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
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    operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
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      -- multiplier side connections (width-bit parallel)
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    core_clk        : in std_logic;
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    result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
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    operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
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    write_result    : in std_logic; -- write enable for multiplier side
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    result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
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  );
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end operand_ram_gen;
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architecture Behavioral of operand_ram_gen is
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  constant nrRAMs : integer := width/32;
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  constant RAMselect_aw : integer := log2(nrRAMs);
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  constant RAMdepth_aw : integer := log2(depth);
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  constant total_aw : integer := RAMdepth_aw+RAMselect_aw;
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  -- total RAM structure signals
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  signal weA_RAM : std_logic_vector(nrRAMs-1 downto 0);
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  type wordsplit is array (nrRAMs-1 downto 0) of std_logic_vector(31 downto 0);
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  signal doutA_RAM : wordsplit;
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  --- PORT A : 32-bit write | (width)-bit read
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  signal dinA    : std_logic_vector(31 downto 0);
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  signal doutA   : std_logic_vector(31 downto 0);
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  signal weA     : std_logic;
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  signal addrA   : std_logic_vector(RAMselect_aw-1 downto 0);
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  signal op_selA : std_logic_vector(RAMdepth_aw-1 downto 0);
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  --- PORT B : 32-bit read  | (width)-bit write
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  signal dinB    : std_logic_vector(width-1 downto 0);
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  signal doutB   : std_logic_vector(width-1 downto 0);
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  signal weB     : std_logic;
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  signal addrB   : std_logic_vector(RAMselect_aw-1 downto 0);
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  signal op_selB : std_logic_vector(RAMdepth_aw-1 downto 0);
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  signal write_operand_i : std_logic;
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  signal op_selB_i : std_logic_vector(RAMdepth_aw-1 downto 0);
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begin
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        -- WARNING: Very Important!
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  -- wea & web signals must never be high at the same time !!
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  -- web has priority 
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  write_operand_i <= write_operand and not write_result; -- portB has write priority
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  collision <= write_operand and write_result;
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  -- the dual port ram has a depth of 4 (each layer contains an operand)
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  -- result is always stored in position 3
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  -- doutb is always result
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  with write_result select
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    op_selB_i <= result_dest_op when '1',
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                 operand_out_sel when others;
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  -- map signals to RAM
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  -- PORTA
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  weA <= write_operand_i;
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  op_selA <= operand_in_sel;
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  addrA <= operand_addr;
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  dinA <= operand_in;
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  result_out <= doutA;
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  -- PORT B
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  weB <= write_result;
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  op_selB <= op_selB_i; -- portB locked to result operand
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  addrB <= operand_addr;
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  dinB <= result_in;
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  operand_out <= doutB;
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        -- generate (width/32) blocks of 32-bit ram with a given depth
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  -- these rams are tyed together to form the following structure
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  --  True dual port ram:
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  --  - PORT A : 32-bit write | 32-bit read
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  --  - PORT B : (width)-bit read  | (width)-bit write
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  --                ^             ^
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  -- addres       addr          op_sel
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  -- 
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  ramblocks : for i in 0 to nrRAMs-1 generate
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    ramblock: tdpram_generic
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    generic map(
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      depth => depth
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    )
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    port map(
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      -- port A : 32-bit
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      clkA  => bus_clk,
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      addrA => op_selA,
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      weA   => weA_RAM(i),
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      dinA  => dinA,
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      doutA => doutA_RAM(i),
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      -- port B : 32-bit
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      clkB  => core_clk,
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      addrB => op_selB,
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      weB   => weB,
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      dinB  => dinB(((i+1)*32)-1 downto i*32),
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      doutB => doutB(((i+1)*32)-1 downto i*32)
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    );
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    --    demultiplexer for write enable A signal
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    process (addrA, weA)
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    begin
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      if addrA(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
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        weA_RAM(i) <= weA;
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      else
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        weA_RAM(i) <= '0';
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      end if;
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    end process;
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  end generate;
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  -- PORTB 32-bit read
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  doutA <= doutA_RAM(conv_integer(addrA)) when (conv_integer(addrA)<nrRAMs)
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          else (others=>'0');
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end Behavioral;

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