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---- pulse_cdc ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- transfers a pulse (1clk wide) from clock domain A to ----
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---- clock domain B by using a toggling signal. This design ----
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---- avoids metastable states ----
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---- ----
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---- Dependencies: none ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity pulse_cdc is
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port (
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reset : in std_logic;
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clkA : in std_logic;
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pulseA : in std_logic;
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clkB : in std_logic;
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pulseB : out std_logic
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);
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end pulse_cdc;
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architecture arch of pulse_cdc is
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signal pulseA_d : std_logic;
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signal toggle : std_logic := '0';
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signal toggle_d, toggle_d2, toggle_d3 : std_logic;
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begin
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-- Convert pulse from clock domain A to a toggling signal
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PulseAtoToggle : process (clkA, reset)
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begin
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if reset='1' then
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toggle <= '0';
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else
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if rising_edge(clkA) then
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pulseA_d <= pulseA;
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toggle <= toggle xor (pulseA and not pulseA_d);
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end if;
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end if;
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end process;
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-- Convert toggling signal to a pulse of 1clk wide to clock domain B
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ToggletoPulseB : process (clkB, reset)
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begin
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if reset='1' then
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toggle_d <= '0';
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toggle_d2 <= '0';
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toggle_d3 <= '0';
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else
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if rising_edge(clkB) then
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toggle_d <= toggle; -- this signal may have metastability isues
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toggle_d2 <= toggle_d; -- stable now
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toggle_d3 <= toggle_d2;
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end if;
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end if;
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end process;
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pulseB <= toggle_d2 xor toggle_d3;
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end arch;
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