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JonasDC |
----------------------------------------------------------------------
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---- register_1b ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- 1 bit register ----
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---- used in montgommery multiplier systolic array stages ----
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---- ----
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---- Dependencies: none ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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2 |
JonasDC |
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3 |
JonasDC |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- Xilinx primitives used
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JonasDC |
library UNISIM;
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use UNISIM.VComponents.all;
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JonasDC |
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JonasDC |
entity register_1b is
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JonasDC |
port(
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core_clk : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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din : in std_logic;
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dout : out std_logic
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);
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JonasDC |
end register_1b;
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JonasDC |
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JonasDC |
architecture Structural of register_1b is
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signal dout_i : std_logic;
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begin
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dout <= dout_i;
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JonasDC |
FDCE_inst : FDCE
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generic map (
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INIT => '0' -- Initial value of latch ('0' or '1')
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)
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port map (
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Q => dout_i, -- Data output
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CLR => reset, -- Asynchronous clear/reset input
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D => din, -- Data input
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C => core_clk, -- Gate input
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CE => ce -- Gate enable input
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);
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JonasDC |
end Structural;
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