OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_1b.vhd] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 JonasDC
----------------------------------------------------------------------  
2
----  register_1b                                                 ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9 6 JonasDC
----    1 bit register with active high asynchronious reset and ce----
10 3 JonasDC
----    used in montgommery multiplier systolic array stages      ----            
11
----                                                              ---- 
12
----  Dependencies: none                                          ----
13
----                                                              ----
14
----  Authors:                                                    ----
15
----      - Geoffrey Ottoy, DraMCo research group                 ----
16
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
17
----                                                              ---- 
18
---------------------------------------------------------------------- 
19
----                                                              ---- 
20
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
21
----                                                              ---- 
22
---- This source file may be used and distributed without         ---- 
23
---- restriction provided that this copyright statement is not    ---- 
24
---- removed from the file and that any derivative work contains  ---- 
25
---- the original copyright notice and the associated disclaimer. ---- 
26
----                                                              ---- 
27
---- This source file is free software; you can redistribute it   ---- 
28
---- and/or modify it under the terms of the GNU Lesser General   ---- 
29
---- Public License as published by the Free Software Foundation; ---- 
30
---- either version 2.1 of the License, or (at your option) any   ---- 
31
---- later version.                                               ---- 
32
----                                                              ---- 
33
---- This source is distributed in the hope that it will be       ---- 
34
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
35
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
36
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
37
---- details.                                                     ---- 
38
----                                                              ---- 
39
---- You should have received a copy of the GNU Lesser General    ---- 
40
---- Public License along with this source; if not, download it   ---- 
41
---- from http://www.opencores.org/lgpl.shtml                     ---- 
42
----                                                              ---- 
43
----------------------------------------------------------------------
44 2 JonasDC
 
45 3 JonasDC
library ieee;
46
use ieee.std_logic_1164.all;
47
use ieee.std_logic_arith.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 6 JonasDC
-- 1-bit register with asynchronous reset and clock enable
51 2 JonasDC
entity register_1b is
52 3 JonasDC
  port(
53 6 JonasDC
    core_clk : in  std_logic; -- clock input
54
    ce       : in  std_logic; -- clock enable (active high)
55
    reset    : in  std_logic; -- reset (active high)
56
    din      : in  std_logic; -- data in
57
    dout     : out std_logic  -- data out
58 3 JonasDC
  );
59 2 JonasDC
end register_1b;
60
 
61 3 JonasDC
 
62 6 JonasDC
architecture Behavorial of register_1b is
63 2 JonasDC
begin
64
 
65 6 JonasDC
        -- process for 1-bit register
66
  reg_1b : process (reset, ce, core_clk, din)
67
  begin
68
    if reset='1' then -- asynchronous active high reset
69
      dout <= '0';
70
    else
71
      if rising_edge(core_clk) then -- clock in data on rising edge
72
        if ce='1' then  -- active high clock enable to clock in data
73
          dout <= din;
74
        end if;
75
      end if;
76
    end if;
77
  end process;
78 3 JonasDC
 
79 6 JonasDC
end Behavorial;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.