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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Blame information for rev 7

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1 3 JonasDC
----------------------------------------------------------------------  
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----  register_n                                                  ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    n bit register with active high asynchronious reset and ce----
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----    used in montgommery multiplier systolic array stages      ----            
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----                                                              ---- 
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----  Dependencies: none                                          ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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45 3 JonasDC
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- n-bit register with asynchronous reset and clock enable
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entity register_n is
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  generic(
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    n : integer := 4
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  );
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  port(
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    core_clk : in  std_logic; -- clock input
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    ce       : in  std_logic; -- clock enable (active high)
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    reset    : in  std_logic; -- reset (active high)
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    din      : in  std_logic_vector((n-1) downto 0);  -- data in (n-bit)
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    dout     : out std_logic_vector((n-1) downto 0)   -- data out (n-bit)
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  );
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end register_n;
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architecture Behavorial of register_n is
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begin
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         -- process for n-bit register
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  reg_nb : process (reset, ce, core_clk, din)
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  begin
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    if reset='1' then -- asynchronous active high reset
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      dout <= (others=>'0');
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    else
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      if rising_edge(core_clk) then -- clock in data on rising edge
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        if ce='1' then  -- active high clock enable to clock in data
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          dout <= din;
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        end if;
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      end if;
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    end if;
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  end process;
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end Behavorial;

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