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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [standard_cell_block.vhd] - Blame information for rev 17

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1 3 JonasDC
----------------------------------------------------------------------  
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----  standard_cell_block                                         ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    a block of (width) cell_1b cells for use in the           ----
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----    montgommery multiplier systolic array                     ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - cell_1b                                                 ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- a standard cell block of (width)-bit for the montgommery multiplier 
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-- systolic array
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entity standard_cell_block is
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  generic (
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    width : integer := 16
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  );
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  port (
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    -- modulus and y operand input (width)-bit
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    my   : in  std_logic_vector((width-1) downto 0);
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    y    : in  std_logic_vector((width-1) downto 0);
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    m    : in  std_logic_vector((width-1) downto 0);
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    -- q and x operand input (serial input)
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    x    : in  std_logic;
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    q    : in  std_logic;
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    -- previous result in (width)-bit
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    a    : in  std_logic_vector((width-1) downto 0);
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    -- carry in and out
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    cin  : in std_logic;
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    cout : out std_logic;
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    -- result out (width)-bit
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    r    : out  std_logic_vector((width-1) downto 0)
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  );
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end standard_cell_block;
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architecture Structural of standard_cell_block is
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  -- vector for the carry bits
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        signal carry : std_logic_vector(width downto 0);
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begin
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        -- carry in
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        carry(0) <= cin;
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        -- structure of (width) 1-bit cells
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  cell_block : for i in 0 to (width-1) generate
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    cells : cell_1b
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    port map(
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      my   => my(i),
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      y    => y(i),
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      m    => m(i),
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      x    => x,
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      q    => q,
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      a    => a(i),
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      cin  => carry(i),
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      cout => carry(i+1),
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      r    => r(i)
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    );
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  end generate;
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  -- carry out
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        cout <= carry(width);
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end Structural;

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