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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [sys_first_cell_logic.vhd] - Blame information for rev 31

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1 31 JonasDC
----------------------------------------------------------------------  
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----  sys_first_cell_logic                                        ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    first cell logic for use int the montogommery mulitplier  ----
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----    pipelined systolic array                                  ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - register_n                                              ----
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----    - cell_1b_adder                                           ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- logic needed as the first piece in the systolic array pipeline
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-- calculates the first my_cout and generates q signal
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entity sys_first_cell_logic is
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  port  (
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    m0       : in std_logic;    -- lsb from m operand
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    y0       : in std_logic;    -- lsb from y operand
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    my_cout  : out std_logic;   -- my_cin for first stage
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    xi       : in std_logic;    -- xi operand input
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    xout     : out std_logic;   -- xin for first stage
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    qout     : out std_logic;   -- qin for first stage
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    cout     : out std_logic;   -- cin for first stage
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    a_0      : in std_logic;    -- a_0 from first stage
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    red_cout : out std_logic    -- red_cin for first stage
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  );
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end sys_first_cell_logic;
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architecture Behavorial of sys_first_cell_logic is
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  -- first cell signals
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  signal my0_mux_result : std_logic;
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  signal my0 : std_logic;
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  signal qout_i : std_logic;
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begin
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  -- half adder for m0 +y0
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  my0 <= m0 xor y0;
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  my_cout <= m0 and y0; -- carry
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  xout <= xi;
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  qout_i <= (xi and y0) xor a_0;
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  cout <= my0_mux_result and a_0;
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  red_cout <= '1'; -- add 1 for 2s complement
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  my0_mux : cell_1b_mux
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  port map(
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    my     => my0,
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    m      => m0,
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    y      => y0,
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    x      => xi,
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    q      => qout_i,
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    result => my0_mux_result
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  );
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  qout <= qout_i;
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end Behavorial;

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