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---- sys_last_cell_logic ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- last cell logic for use int the montogommery mulitplier ----
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---- pipelined systolic array ----
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---- ----
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---- Dependencies: ----
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---- - register_n ----
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---- - cell_1b_adder ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- logic needed as the last piece in the systolic array pipeline
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-- calculates the last 2 bits of the cell_result and finishes the reduction
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-- also generates the result selection signal
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entity sys_last_cell_logic is
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port (
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core_clk : in std_logic; -- clock input
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reset : in std_logic;
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a_0 : out std_logic; -- a_msb for last stage
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cin : in std_logic; -- cout from last stage
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red_cin : in std_logic; -- red_cout from last stage
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r_sel : out std_logic; -- result selection bit
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start : in std_logic -- done signal from last stage
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);
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end sys_last_cell_logic;
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architecture Behavorial of sys_last_cell_logic is
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signal cell_result_high : std_logic_vector(1 downto 0);
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signal cell_result_high_reg : std_logic_vector(1 downto 0);
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signal red_cout_end : std_logic;
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begin
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-- half adder: cout_last_stage + cell_result_high_reg(1)
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cell_result_high(0) <= cin xor cell_result_high_reg(1); --result
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cell_result_high(1) <= cin and cell_result_high_reg(1); --cout
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a_0 <= cell_result_high_reg(0);
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last_reg : register_n
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generic map(
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width => 2
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)
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port map(
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core_clk => core_clk,
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ce => start,
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reset => reset,
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din => cell_result_high,
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dout => cell_result_high_reg
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);
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-- reduction, finishing last 2 bits
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reduction_adder_a : cell_1b_adder
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port map(
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a => '1', -- for 2s complement of m
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b => cell_result_high_reg(0),
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cin => red_cin,
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cout => red_cout_end
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);
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reduction_adder_b : cell_1b_adder
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port map(
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a => '1', -- for 2s complement of m
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b => cell_result_high_reg(1),
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cin => red_cout_end,
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cout => r_sel
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);
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end Behavorial;
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