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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [sys_pipeline.vhd] - Blame information for rev 37

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1 25 JonasDC
----------------------------------------------------------------------  
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----  sys_pipeline                                                ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    the pipelined systolic array for a montgommery multiplier ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - sys_stage                                               ----
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----    - register_n                                              ----
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----    - d_flip_flop                                             ----
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----    - cell_1b_adder                                           ----
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----    - cell_1b_mux                                             ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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53
library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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56
-- the pipelined systolic array for a montgommery multiplier
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-- contains a structural description of the pipeline using the systolic stages
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entity sys_pipeline is
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        generic(
60
    n  : integer := 1536; -- width of the operands (# bits)
61 37 JonasDC
    t  : integer := 192;  -- total number of stages (minimum 2)
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    tl : integer := 64;   -- lower number of stages (minimum 1)
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    split : boolean := true -- if true the pipeline wil be split in 2 parts,
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                            -- if false there are no lower stages, only t counts
65 25 JonasDC
  );
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  port(
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    -- clock input
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    core_clk : in  std_logic;
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    -- modulus and y opperand input (n)-bit
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    y        : in  std_logic_vector((n-1) downto 0);
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    m        : in  std_logic_vector((n-1) downto 0);
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    -- x operand input (serial)
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    xi       : in  std_logic;
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    next_x   : out std_logic; -- next x operand bit
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    -- control signals
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    start    : in  std_logic; -- start multiplier
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    reset    : in  std_logic;
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    p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
79
    -- result out
80
    r        : out std_logic_vector((n-1) downto 0)
81
  );
82
end sys_pipeline;
83
 
84
architecture Structural of sys_pipeline is
85
  constant s : integer := n/t;
86
 
87 37 JonasDC
  signal m_i     : std_logic_vector(n downto 0);
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  signal y_i     : std_logic_vector(n downto 0);
89 25 JonasDC
 
90 37 JonasDC
  -- systolic stages signals
91
  signal my_cin_stage   : std_logic_vector((t-1) downto 0);
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  signal my_cout_stage  : std_logic_vector((t-1) downto 0);
93
  signal xin_stage      : std_logic_vector((t-1) downto 0);
94
  signal qin_stage      : std_logic_vector((t-1) downto 0);
95
  signal xout_stage     : std_logic_vector((t-1) downto 0);
96
  signal qout_stage     : std_logic_vector((t-1) downto 0);
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  signal a_msb_stage    : std_logic_vector((t-1) downto 0);
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  signal a_0_stage      : std_logic_vector((t-1) downto 0);
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  signal cin_stage      : std_logic_vector((t-1) downto 0);
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  signal cout_stage     : std_logic_vector((t-1) downto 0);
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  signal red_cin_stage  : std_logic_vector((t-1) downto 0);
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  signal red_cout_stage : std_logic_vector((t-1) downto 0);
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  signal start_stage    : std_logic_vector((t-1) downto 0);
104
  signal done_stage     : std_logic_vector((t-1) downto 0);
105
  signal r_sel_stage    : std_logic_vector((t-1) downto 0);
106
 
107
  -- end logic signals
108
  signal r_sel_end : std_logic;
109
 
110
  -- signals needed if pipeline is split
111
  ---------------------------------------
112 36 JonasDC
  signal r_sel_l : std_logic;
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  signal r_sel_h : std_logic;
114 37 JonasDC
  -- mid end logic signals
115
  signal a_0_midend   : std_logic;
116 32 JonasDC
  signal r_sel_midend : std_logic;
117 25 JonasDC
 
118 37 JonasDC
  -- mid start logic signals
119
  signal my_cout_midstart   : std_logic;
120
  signal xout_midstart      : std_logic;
121
  signal qout_midstart      : std_logic;
122
  signal cout_midstart      : std_logic;
123
  signal red_cout_midstart  : std_logic;
124 32 JonasDC
 
125 37 JonasDC
 
126 25 JonasDC
begin
127
 
128
  m_i <= '0' & m;
129
  y_i <= '0' & y;
130
 
131
  -- generate the stages for the full pipeline
132
  pipeline_stages : for i in 0 to (t-1) generate
133
    stage : sys_stage
134
    generic map(
135
      width => s
136
    )
137
    port map(
138
      core_clk => core_clk,
139
      y        => y_i((i+1)*s downto (i*s)+1),
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      m        => m_i((i+1)*s downto (i*s)),
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      my_cin   => my_cin_stage(i),
142
      my_cout  => my_cout_stage(i),
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      xin      => xin_stage(i),
144
      qin      => qin_stage(i),
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      xout     => xout_stage(i),
146
      qout     => qout_stage(i),
147
      a_0      => a_0_stage(i),
148
      a_msb    => a_msb_stage(i),
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      cin      => cin_stage(i),
150
      cout     => cout_stage(i),
151
      red_cin  => red_cin_stage(i),
152
      red_cout => red_cout_stage(i),
153
      start    => start_stage(i),
154
      reset    => reset,
155
      done     => done_stage(i),
156 36 JonasDC
      r_sel    => r_sel_stage(i),
157 25 JonasDC
      r        => r(((i+1)*s)-1 downto (i*s))
158
    );
159
  end generate;
160
 
161
  -- first cell logic
162
  --------------------
163 32 JonasDC
  first_cell : sys_first_cell_logic
164 31 JonasDC
  port map (
165
    m0       => m_i(0),
166
    y0       => y_i(0),
167
    my_cout  => my_cin_stage(0),
168
    xi       => xi,
169
    xout     => xin_stage(0),
170
    qout     => qin_stage(0),
171
    cout     => cin_stage(0),
172
    a_0      => a_0_stage(0),
173
    red_cout => red_cin_stage(0)
174 25 JonasDC
  );
175
 
176 37 JonasDC
    -- last cell logic
177
  -------------------
178
  last_cell : sys_last_cell_logic
179
  port map (
180
    core_clk => core_clk,
181
    reset    => reset,
182
    a_0      => a_msb_stage(t-1),
183
    cin      => cout_stage(t-1),
184
    red_cin  => red_cout_stage(t-1),
185
    r_sel    => r_sel_end,
186
    start    => done_stage(t-1)
187
  );
188
 
189
------------------------------------
190
-- SINGLE PART PIPELINE CONNECTIONS
191
------------------------------------
192
single_pipeline : if split=false generate
193
  -- link stages to eachother
194
  stage_connect : for i in 1 to (t-1) generate
195
    my_cin_stage(i) <= my_cout_stage(i-1);
196
    cin_stage(i) <= cout_stage(i-1);
197
    xin_stage(i) <= xout_stage(i-1);
198
    qin_stage(i) <= qout_stage(i-1);
199
    red_cin_stage(i) <= red_cout_stage(i-1);
200
    start_stage(i) <= done_stage(i-1);
201
    a_msb_stage(i-1) <= a_0_stage(i);
202
    r_sel_stage(i) <= r_sel_end;
203
  end generate;
204
    r_sel_stage(0) <= r_sel_end;
205
 
206
  start_stage(0) <= start;
207
  next_x <= done_stage(0);
208
end generate;
209
 
210
----------------------------------------
211
-- SPLIT PIPELINE CONNECTIONS AND LOGIC
212
----------------------------------------
213
split_pipeline : if split=true generate
214 32 JonasDC
  -- only start first stage if lower part is used
215
  with p_sel select
216
    start_stage(0) <= '0' when "10",
217
                      start when others;
218 25 JonasDC
 
219 37 JonasDC
  -- select start or midstart stage for requesting new xi bit
220 32 JonasDC
  with p_sel select
221
    next_x <= done_stage(tl) when "10",
222
              done_stage(0) when others;
223
 
224
  -- link lower stages to eachother
225
  stage_connect_l : for i in 1 to (tl-1) generate
226
    my_cin_stage(i) <= my_cout_stage(i-1);
227
    cin_stage(i) <= cout_stage(i-1);
228
    xin_stage(i) <= xout_stage(i-1);
229
    qin_stage(i) <= qout_stage(i-1);
230
    red_cin_stage(i) <= red_cout_stage(i-1);
231
    start_stage(i) <= done_stage(i-1);
232
    a_msb_stage(i-1) <= a_0_stage(i);
233 36 JonasDC
    r_sel_stage(i) <= r_sel_l;
234 32 JonasDC
  end generate;
235 36 JonasDC
    r_sel_stage(0) <= r_sel_l;
236 32 JonasDC
 
237
  -- mid end logic
238
  -----------------
239
  mid_end_cell : sys_last_cell_logic
240
  port map (
241
    core_clk => core_clk,
242
    reset    => reset,
243
    a_0      => a_0_midend,
244
    cin      => cout_stage(tl-1),
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    red_cin  => red_cout_stage(tl-1),
246
    r_sel    => r_sel_midend,
247
    start    => done_stage(tl-1)
248
  );
249
  --muxes for midend signals
250
  with p_sel select
251
    a_msb_stage(tl-1) <= a_0_midend when "01",
252
                         a_0_stage(tl) when others;
253
 
254
  -- mid start logic
255
  -------------------
256
  mid_start_logic : sys_first_cell_logic
257
  port map (
258
    m0       => m_i(tl*s),
259
    y0       => y_i(tl*s),
260
    my_cout  => my_cout_midstart,
261
    xi       => xi,
262
    xout     => xout_midstart,
263
    qout     => qout_midstart,
264
    cout     => cout_midstart,
265
    a_0      => a_0_stage(tl),
266
    red_cout => red_cout_midstart
267
  );
268
 
269
  -- only start stage tl if only higher part is used
270
  with p_sel select
271
    start_stage(tl) <= start when "10",
272
                       done_stage(tl-1) when "11",
273
                       '0' when others;
274
 
275
  with p_sel select
276
    my_cin_stage(tl) <= my_cout_midstart when "10",
277
                        my_cout_stage(tl-1) when others;
278
  with p_sel select
279
    xin_stage(tl) <= xout_midstart when "10",
280
                     xout_stage(tl-1) when others;
281
  with p_sel select
282
    qin_stage(tl) <= qout_midstart when "10",
283
                     qout_stage(tl-1) when others;
284
  with p_sel select
285
    cin_stage(tl) <= cout_midstart when "10",
286
                     cout_stage(tl-1) when others;
287
  with p_sel select
288
    red_cin_stage(tl) <= red_cout_midstart when "10",
289
                         red_cout_stage(tl-1) when others;
290
 
291
    -- link higher stages to eachother
292
  stage_connect_h : for i in (tl+1) to (t-1) generate
293
    my_cin_stage(i) <= my_cout_stage(i-1);
294
    cin_stage(i) <= cout_stage(i-1);
295
    xin_stage(i) <= xout_stage(i-1);
296
    qin_stage(i) <= qout_stage(i-1);
297
    red_cin_stage(i) <= red_cout_stage(i-1);
298
    start_stage(i) <= done_stage(i-1);
299
    a_msb_stage(i-1) <= a_0_stage(i);
300 36 JonasDC
    r_sel_stage(i) <= r_sel_h;
301 32 JonasDC
  end generate;
302 36 JonasDC
    r_sel_stage(tl) <= r_sel_h;
303 25 JonasDC
 
304 32 JonasDC
  with p_sel select
305 36 JonasDC
    r_sel_l <= r_sel_midend when "01",
306
               r_sel_end when "11",
307
               '0' when others;
308
 
309
  with p_sel select
310
    r_sel_h <= '0' when "01",
311
               r_sel_end when others;
312 37 JonasDC
end generate;
313
 
314 25 JonasDC
end Structural;

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