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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [x_shift_reg.vhd] - Blame information for rev 21

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1 3 JonasDC
----------------------------------------------------------------------  
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----  x_shift_reg                                                 ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    n bit shift register for the x operand of the multiplier  ----
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----    with bit output                                           ----
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----                                                              ---- 
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----  Dependencies: none                                          ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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45 3 JonasDC
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- shift register for the x operand of the multiplier
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-- outputs the lsb of the register or bit at offset according to the
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-- selected pipeline part 
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entity x_shift_reg is
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  generic(
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    n  : integer := 1536; -- width of the operands (# bits)
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    t  : integer := 48;   -- total number of stages
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    tl : integer := 16    -- lower number of stages
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  );
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  port(
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    -- clock input
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    clk    : in  std_logic;
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    -- x operand in (n-bit)
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    x_in   : in  std_logic_vector((n-1) downto 0);
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    -- control signals
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    reset  : in  std_logic; -- reset, clears register
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    load_x : in  std_logic; -- load operand into shift register   
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    next_x : in  std_logic; -- next bit of x
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    p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
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    -- x operand bit out (serial)
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    xi     : out std_logic
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  );
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end x_shift_reg;
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architecture Behavioral of x_shift_reg is
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  signal x_reg  : std_logic_vector((n-1) downto 0); -- register
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  constant s      : integer := n/t;   -- stage width
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  constant offset : integer := s*tl;  -- calculate startbit pos of higher part of pipeline
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begin
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        REG_PROC: process(reset, clk)
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        begin
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                if reset = '1' then -- Reset, clear the register
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                        x_reg <= (others => '0');
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                elsif rising_edge(clk) then
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                        if load_x = '1' then -- Load_x, load the register with x_in
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                                x_reg <= x_in;
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                        elsif next_x = '1' then  -- next_x, shift to right. LSbit gets lost and zero's are shifted in
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                                x_reg((n-2) downto 0) <= x_reg((n-1) downto 1);
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                        else -- else remember state
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                                x_reg <= x_reg;
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                        end if;
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                end if;
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        end process;
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        with p_sel select  -- pipeline select
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                xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
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                                  x_reg(0) when others;    -- use LS bit for lower part of pipeline
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end Behavioral;

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