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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Blame information for rev 84

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1 84 JonasDC
----------------------------------------------------------------------  
2
----  msec_ipcore_axilite                                         ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    AXI-Lite bus interface for the mod_sim_exp_core. Has a    ----
10
----    fixed address decoder, address offsets are:               ----
11
----                                                              ----
12
----      M       : 0xXXXX0000                                    ----
13
----      OP0     : 0xXXXX1000                                    ----
14
----      OP1     : 0xXXXX2000                                    ----
15
----      OP2     : 0xXXXX3000                                    ----
16
----      OP3     : 0xXXXX4000                                    ----
17
----      FIFO    : 0xXXXX5000                                    ----
18
----      Control : 0xXXXX6000                                    ----
19
----                                                              ----
20
----    only the XXXX part of the address can be chosen freely    ----
21
----                                                              ----
22
----  Dependencies:                                               ----
23
----    - mod_sim_exp_core                                        ----
24
----                                                              ----
25
----  Authors:                                                    ----
26
----      - Geoffrey Ottoy, DraMCo research group                 ----
27
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
28
----                                                              ---- 
29
---------------------------------------------------------------------- 
30
----                                                              ---- 
31
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
32
----                                                              ---- 
33
---- This source file may be used and distributed without         ---- 
34
---- restriction provided that this copyright statement is not    ---- 
35
---- removed from the file and that any derivative work contains  ---- 
36
---- the original copyright notice and the associated disclaimer. ---- 
37
----                                                              ---- 
38
---- This source file is free software; you can redistribute it   ---- 
39
---- and/or modify it under the terms of the GNU Lesser General   ---- 
40
---- Public License as published by the Free Software Foundation; ---- 
41
---- either version 2.1 of the License, or (at your option) any   ---- 
42
---- later version.                                               ---- 
43
----                                                              ---- 
44
---- This source is distributed in the hope that it will be       ---- 
45
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
46
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
47
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
48
---- details.                                                     ---- 
49
----                                                              ---- 
50
---- You should have received a copy of the GNU Lesser General    ---- 
51
---- Public License along with this source; if not, download it   ---- 
52
---- from http://www.opencores.org/lgpl.shtml                     ---- 
53
----                                                              ---- 
54
----------------------------------------------------------------------
55 82 JonasDC
 
56
library ieee;
57
use ieee.std_logic_1164.all;
58
use ieee.std_logic_arith.all;
59
use ieee.std_logic_unsigned.all;
60
 
61
library mod_sim_exp;
62
use mod_sim_exp.mod_sim_exp_pkg;
63
 
64
------------------------------------------------------------------------------
65
-- Entity section
66
------------------------------------------------------------------------------
67
-- Definition of Generics:
68
--   C_S_AXI_DATA_WIDTH           -- AXI4LITE slave: Data width
69
--   C_S_AXI_ADDR_WIDTH           -- AXI4LITE slave: Address Width
70
--   C_BASEADDR                   -- AXI4LITE slave: base address
71
--   C_HIGHADDR                   -- AXI4LITE slave: high address
72
--
73
-- Definition of Ports:
74
--   S_AXI_ACLK                   -- AXI4LITE slave: Clock 
75
--   S_AXI_ARESETN                -- AXI4LITE slave: Reset
76
--   S_AXI_AWADDR                 -- AXI4LITE slave: Write address
77
--   S_AXI_AWVALID                -- AXI4LITE slave: Write address valid
78
--   S_AXI_WDATA                  -- AXI4LITE slave: Write data
79
--   S_AXI_WSTRB                  -- AXI4LITE slave: Write strobe
80
--   S_AXI_WVALID                 -- AXI4LITE slave: Write data valid
81
--   S_AXI_BREADY                 -- AXI4LITE slave: Response ready
82
--   S_AXI_ARADDR                 -- AXI4LITE slave: Read address
83
--   S_AXI_ARVALID                -- AXI4LITE slave: Read address valid
84
--   S_AXI_RREADY                 -- AXI4LITE slave: Read data ready
85
--   S_AXI_ARREADY                -- AXI4LITE slave: read addres ready
86
--   S_AXI_RDATA                  -- AXI4LITE slave: Read data
87
--   S_AXI_RRESP                  -- AXI4LITE slave: Read data response
88
--   S_AXI_RVALID                 -- AXI4LITE slave: Read data valid
89
--   S_AXI_WREADY                 -- AXI4LITE slave: Write data ready
90
--   S_AXI_BRESP                  -- AXI4LITE slave: Response
91
--   S_AXI_BVALID                 -- AXI4LITE slave: Resonse valid
92
--   S_AXI_AWREADY                -- AXI4LITE slave: Wrte address ready
93
------------------------------------------------------------------------------
94
 
95 84 JonasDC
entity msec_ipcore_axilite is
96
  generic(
97
    -- Multiplier parameters
98 82 JonasDC
    C_NR_BITS_TOTAL   : integer := 1536;
99
    C_NR_STAGES_TOTAL : integer := 96;
100
    C_NR_STAGES_LOW   : integer := 32;
101
    C_SPLIT_PIPELINE  : boolean := true;
102
    C_FIFO_DEPTH      : integer := 32;
103 84 JonasDC
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
104
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
105
    -- Bus protocol parameters
106 82 JonasDC
    C_S_AXI_DATA_WIDTH             : integer              := 32;
107
    C_S_AXI_ADDR_WIDTH             : integer              := 32;
108
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
109
    C_HIGHADDR                     : std_logic_vector     := X"00000000"
110
  );
111 84 JonasDC
  port(
112 82 JonasDC
    --USER ports
113
    calc_time                     : out std_logic;
114
    IntrEvent                     : out std_logic;
115
    -------------------------
116
    -- AXI4lite interface
117
    -------------------------
118
    --- Global signals
119
    S_AXI_ACLK                     : in  std_logic;
120
    S_AXI_ARESETN                  : in  std_logic;
121
    --- Write address channel
122
    S_AXI_AWADDR                   : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
123
    S_AXI_AWVALID                  : in  std_logic;
124
    S_AXI_AWREADY                  : out std_logic;
125
    --- Write data channel
126
    S_AXI_WDATA                    : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
127
    S_AXI_WVALID                   : in  std_logic;
128
    S_AXI_WREADY                   : out std_logic;
129
    S_AXI_WSTRB                    : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
130
    --- Write response channel
131
    S_AXI_BVALID                   : out std_logic;
132
    S_AXI_BREADY                   : in  std_logic;
133
    S_AXI_BRESP                    : out std_logic_vector(1 downto 0);
134
    --- Read address channel
135
    S_AXI_ARADDR                   : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
136
    S_AXI_ARVALID                  : in  std_logic;
137
    S_AXI_ARREADY                  : out std_logic;
138
    --- Read data channel
139
    S_AXI_RDATA                    : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
140
    S_AXI_RVALID                   : out std_logic;
141
    S_AXI_RREADY                   : in  std_logic;
142
    S_AXI_RRESP                    : out std_logic_vector(1 downto 0)
143
  );
144
 
145
  attribute MAX_FANOUT : string;
146
  attribute SIGIS      : string;
147
  attribute MAX_FANOUT of S_AXI_ACLK    : signal is "10000";
148
  attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
149
  attribute SIGIS of S_AXI_ACLK         : signal is "Clk";
150
  attribute SIGIS of S_AXI_ARESETN      : signal is "Rst";
151 84 JonasDC
end entity msec_ipcore_axilite;
152 82 JonasDC
 
153
------------------------------------------------------------------------------
154
-- Architecture section
155
------------------------------------------------------------------------------
156
 
157 84 JonasDC
architecture IMP of msec_ipcore_axilite is
158 82 JonasDC
  type axi_states is (addr_wait, read_state, write_state, response_state);
159
  signal state : axi_states;
160
 
161
  signal address : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
162
  signal reset : std_logic;
163
 
164 84 JonasDC
  signal S_AXI_BVALID_i : std_logic;
165 82 JonasDC
 
166
  -- selection signals
167
  signal cs_array           : std_logic_vector(6 downto 0);
168
  signal slv_reg_selected : std_logic;
169
  signal op_mem_selected    : std_logic;
170
  signal op_sel             : std_logic_vector(1 downto 0);
171
  signal MNO_sel            : std_logic;
172
 
173
  -- slave register signals
174
  signal slv_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
175
  signal slv_reg_write_enable : std_logic;
176
  signal load_flags : std_logic;
177
 
178
  -- core interface signeals
179
  signal write_enable : std_logic;
180
  signal core_write_enable : std_logic;
181
  signal core_fifo_push : std_logic;
182
  signal core_data_out : std_logic_vector(31 downto 0);
183
  signal core_rw_address : std_logic_vector(8 downto 0);
184
 
185
  ------------------------------------------------------------------
186
  -- Signals for multiplier core interrupt
187
  ------------------------------------------------------------------
188
  signal core_interrupt                 : std_logic;
189
  signal core_fifo_full                 : std_logic;
190
  signal core_fifo_nopush               : std_logic;
191
  signal core_ready                     : std_logic;
192
  signal core_mem_collision             : std_logic;
193
 
194
  ------------------------------------------------------------------
195
  -- Signals for multiplier core control
196
  ------------------------------------------------------------------
197
  signal core_start                     : std_logic;
198
  signal core_exp_m                     : std_logic;
199
  signal core_p_sel                     : std_logic_vector(1 downto 0);
200
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
201
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
202
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
203
  signal core_flags                     : std_logic_vector(15 downto 0);
204
  signal core_modulus_sel               : std_logic;
205
 
206
begin
207
  -- unused signals
208
  S_AXI_BRESP <= "00";
209
  S_AXI_RRESP <= "00";
210
 
211
  -- axi-lite slave state machine
212
  axi_slave_states : process (S_AXI_ACLK)
213
  begin
214
    if rising_edge(S_AXI_ACLK) then
215
      if S_AXI_ARESETN='0' then -- slave reset state
216
        S_AXI_RVALID <= '0';
217 84 JonasDC
        S_AXI_BVALID_i <= '0';
218 82 JonasDC
        S_AXI_ARREADY <= '0';
219
        S_AXI_WREADY <= '0';
220
        S_AXI_AWREADY <= '0';
221
        state <= addr_wait;
222
        address <= (others=>'0');
223
        write_enable <= '0';
224
      else
225
        case state is
226
          when addr_wait =>
227
          -- wait for a read or write address and latch it in
228
            if S_AXI_ARVALID = '1' then -- read
229
              state <= read_state;
230
              address <= S_AXI_ARADDR;
231
              S_AXI_ARREADY <= '1';
232 84 JonasDC
            elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then -- write
233 82 JonasDC
              state <= write_state;
234
              address <= S_AXI_AWADDR;
235
            else
236
              state <= addr_wait;
237
            end if;
238
 
239
          when read_state =>
240
          -- place correct data on bus and generate valid pulse
241
            S_AXI_ARREADY <= '0';
242
            S_AXI_RVALID <= '1';
243
            state <= response_state;
244
 
245
          when write_state =>
246
          -- generate a write pulse
247 84 JonasDC
            S_AXI_AWREADY <= '1';
248
            write_enable <= '1';
249
            S_AXI_WREADY <= '1';
250
            state <= response_state;
251 82 JonasDC
 
252
          when response_state =>
253
            write_enable <= '0';
254 84 JonasDC
            S_AXI_AWREADY <= '0';
255 82 JonasDC
            S_AXI_WREADY <= '0';
256 84 JonasDC
            S_AXI_BVALID_i <= '1';
257 82 JonasDC
          -- wait for response from master
258 84 JonasDC
            if (S_AXI_RREADY = '1') or (S_AXI_BVALID_i = '1' and S_AXI_BREADY = '1') then
259 82 JonasDC
              S_AXI_RVALID <= '0';
260 84 JonasDC
              S_AXI_BVALID_i <= '0';
261 82 JonasDC
              state <= addr_wait;
262
            else
263
              state <= response_state;
264
            end if;
265
 
266
        end case;
267
      end if;
268
    end if;
269
  end process;
270 84 JonasDC
  S_AXI_BVALID <= S_AXI_BVALID_i;
271
 
272
  -- place correct data on the read bus
273
  S_AXI_RDATA <=  slv_reg when (slv_reg_selected='1') else
274
                  core_data_out;
275 82 JonasDC
 
276
  -- SLAVE REG MAPPING
277
  -- core control signals
278 84 JonasDC
  core_p_sel <= slv_reg(31 downto 30);
279
  core_dest_op_single <= slv_reg(29 downto 28);
280
  core_x_sel_single <= slv_reg(27 downto 26);
281
  core_y_sel_single <= slv_reg(25 downto 24);
282
  core_start <= slv_reg(23);
283
  core_exp_m <= slv_reg(22);
284
  core_modulus_sel <= slv_reg(21);
285
  reset <= (not S_AXI_ARESETN) or slv_reg(20);
286 82 JonasDC
 
287
  -- implement slave register
288
  SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is
289
  begin
290
    if rising_edge(S_AXI_ACLK) then
291
      if S_AXI_ARESETN = '0' then
292
        slv_reg <= (others => '0');
293
      elsif load_flags = '1' then
294 84 JonasDC
        slv_reg <= slv_reg(31 downto 16) & core_flags;
295 82 JonasDC
      else
296
        if (slv_reg_write_enable='1') then
297
          slv_reg <= S_AXI_WDATA(31 downto 0);
298
        end if;
299
      end if;
300
    end if;
301
  end process SLAVE_REG_WRITE_PROC;
302
 
303
  -- interrupt and flags
304
  core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
305 84 JonasDC
  IntrEvent <= core_interrupt;
306 82 JonasDC
 
307
  FLAGS_CNTRL_PROC : process(S_AXI_ACLK, S_AXI_ARESETN) is
308
  begin
309
    if S_AXI_ARESETN = '0' then
310
      core_flags <= (others => '0');
311
      load_flags <= '0';
312
    elsif rising_edge(S_AXI_ACLK) then
313
      if core_start = '1' then
314
        core_flags <= (others => '0');
315
      else
316
        if core_ready = '1' then
317
          core_flags(15) <= '1';
318
        else
319
          core_flags(15) <= core_flags(15);
320
        end if;
321
        if core_mem_collision = '1' then
322
          core_flags(14) <= '1';
323
        else
324
          core_flags(14) <= core_flags(14);
325
        end if;
326
        if core_fifo_full = '1' then
327
          core_flags(13) <= '1';
328
        else
329
          core_flags(13) <= core_flags(13);
330
        end if;
331
        if core_fifo_nopush = '1' then
332
          core_flags(12) <= '1';
333
        else
334
          core_flags(12) <= core_flags(12);
335
        end if;
336
      end if;
337
      load_flags <= core_interrupt;
338
    end if;
339
  end process FLAGS_CNTRL_PROC;
340
 
341
  -- adress decoder
342
  with address(14 downto 12) select
343
    cs_array <= "0000001" when "000", -- M
344
                "0000010" when "001", -- OP0
345
                "0000100" when "010", -- OP1
346
                "0001000" when "011", -- OP2
347
                "0010000" when "100", -- OP3
348
                "0100000" when "101", -- FIFO
349
                "1000000" when "110", -- user reg space
350
                "0000000" when others;
351 84 JonasDC
 
352 82 JonasDC
  slv_reg_selected <= cs_array(6);
353
  slv_reg_write_enable <= write_enable and slv_reg_selected;
354
 
355
  -- high if memory space is selected
356
  op_mem_selected <= cs_array(0) or cs_array(1) or cs_array(2) or cs_array(3) or cs_array(4);
357
 
358
  -- operand memory singals
359
  MNO_sel <= cs_array(0);
360
 
361
  with cs_array(4 downto 1) select
362
    op_sel <=   "00" when "0001",
363
                "01" when "0010",
364
                "10" when "0100",
365
                "11" when "1000",
366
                "00" when others;
367
 
368
  core_rw_address <= MNO_sel & op_sel & address(7 downto 2);
369
 
370
  core_write_enable <= write_enable and op_mem_selected;
371
 
372
 
373
  -- FIFO signals
374
  core_fifo_push <= write_enable and cs_array(5);
375
 
376
  ------------------------------------------
377
  -- Exponentiation core instance
378
  ------------------------------------------
379
  msec: entity mod_sim_exp.mod_sim_exp_core
380
  generic map(
381
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
382
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
383
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
384
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
385
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
386
    C_MEM_STYLE       => C_MEM_STYLE,
387 84 JonasDC
    C_FPGA_MAN        => C_FPGA_MAN
388 82 JonasDC
  )
389
  port map(
390
    clk   => S_AXI_ACLK,
391
    reset => reset,
392
      -- operand memory interface (plb shared memory)
393
    write_enable => core_write_enable,
394
    data_in      => S_AXI_WDATA(31 downto 0),
395
    rw_address   => core_rw_address,
396
    data_out     => core_data_out,
397
    collision    => core_mem_collision,
398
      -- op_sel fifo interface
399
    fifo_din    => S_AXI_WDATA(31 downto 0),
400
    fifo_push   => core_fifo_push,
401
    fifo_full   => core_fifo_full,
402
    fifo_nopush => core_fifo_nopush,
403
      -- ctrl signals
404
    start          => core_start,
405
    exp_m          => core_exp_m,
406
    ready          => core_ready,
407
    x_sel_single   => core_x_sel_single,
408
    y_sel_single   => core_y_sel_single,
409
    dest_op_single => core_dest_op_single,
410
    p_sel          => core_p_sel,
411
    calc_time      => calc_time,
412
    modulus_sel    => core_modulus_sel
413
  );
414
 
415 84 JonasDC
end IMP;

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