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1 2 JonasDC
------------------------------------------------------------------------------
2
-- user_logic.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
--
5
-- ***************************************************************************
6
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
7
-- **                                                                       **
8
-- ** Xilinx, Inc.                                                          **
9
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
10
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
11
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
12
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
13
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
14
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
15
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
16
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
17
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
18
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
19
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
20
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
21
-- ** FOR A PARTICULAR PURPOSE.                                             **
22
-- **                                                                       **
23
-- ***************************************************************************
24
--
25
------------------------------------------------------------------------------
26
-- Filename:          user_logic.vhd
27
-- Version:           2.00.a
28
-- Description:       User logic.
29
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
30
-- VHDL Standard:     VHDL'93
31
------------------------------------------------------------------------------
32
-- Naming Conventions:
33
--   active low signals:                    "*_n"
34
--   clock signals:                         "clk", "clk_div#", "clk_#x"
35
--   reset signals:                         "rst", "rst_n"
36
--   generics:                              "C_*"
37
--   user defined types:                    "*_TYPE"
38
--   state machine next state:              "*_ns"
39
--   state machine current state:           "*_cs"
40
--   combinatorial signals:                 "*_com"
41
--   pipelined or register delay signals:   "*_d#"
42
--   counter signals:                       "*cnt*"
43
--   clock enable signals:                  "*_ce"
44
--   internal version of output port:       "*_i"
45
--   device pins:                           "*_pin"
46
--   ports:                                 "- Names begin with Uppercase"
47
--   processes:                             "*_PROCESS"
48
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
49
------------------------------------------------------------------------------
50
 
51
-- DO NOT EDIT BELOW THIS LINE --------------------
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_arith.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library proc_common_v3_00_a;
58
use proc_common_v3_00_a.proc_common_pkg.all;
59
 
60
-- DO NOT EDIT ABOVE THIS LINE --------------------
61
 
62
--USER libraries added here
63 40 JonasDC
library mod_sim_exp;
64
use mod_sim_exp.mod_sim_exp_core_pkg.all;
65 2 JonasDC
 
66
------------------------------------------------------------------------------
67
-- Entity section
68
------------------------------------------------------------------------------
69
-- Definition of Generics:
70
--   C_SLV_AWIDTH                 -- Slave interface address bus width
71
--   C_SLV_DWIDTH                 -- Slave interface data bus width
72
--   C_NUM_REG                    -- Number of software accessible registers
73
--   C_NUM_MEM                    -- Number of memory spaces
74
--   C_NUM_INTR                   -- Number of interrupt event
75
--
76
-- Definition of Ports:
77
--   Bus2IP_Clk                   -- Bus to IP clock
78
--   Bus2IP_Reset                 -- Bus to IP reset
79
--   Bus2IP_Addr                  -- Bus to IP address bus
80
--   Bus2IP_CS                    -- Bus to IP chip select for user logic memory selection
81
--   Bus2IP_RNW                   -- Bus to IP read/not write
82
--   Bus2IP_Data                  -- Bus to IP data bus
83
--   Bus2IP_BE                    -- Bus to IP byte enables
84
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
85
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
86
--   IP2Bus_Data                  -- IP to Bus data bus
87
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
88
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
89
--   IP2Bus_Error                 -- IP to Bus error response
90
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
91
------------------------------------------------------------------------------
92
 
93
entity user_logic is
94
  generic
95
  (
96
    -- ADD USER GENERICS BELOW THIS LINE ---------------
97
    --USER generics added here
98
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
99
 
100
    -- DO NOT EDIT BELOW THIS LINE ---------------------
101
    -- Bus protocol parameters, do not add to or delete
102
    C_SLV_AWIDTH                   : integer              := 32;
103
    C_SLV_DWIDTH                   : integer              := 32;
104
    C_NUM_REG                      : integer              := 1;
105
    C_NUM_MEM                      : integer              := 6;
106
    C_NUM_INTR                     : integer              := 1
107
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
108
  );
109
  port
110
  (
111
    -- ADD USER PORTS BELOW THIS LINE ------------------
112
    --USER ports added here
113
         calc_time                      : out std_logic;
114
        -- ctrl_sigs                      : out std_logic_vector( downto );
115
    -- ADD USER PORTS ABOVE THIS LINE ------------------
116
 
117
    -- DO NOT EDIT BELOW THIS LINE ---------------------
118
    -- Bus protocol ports, do not add to or delete
119
    Bus2IP_Clk                     : in  std_logic;
120
    Bus2IP_Reset                   : in  std_logic;
121
    Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
122
    Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
123
    Bus2IP_RNW                     : in  std_logic;
124
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
125
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
126
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
127
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
128
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
129
    IP2Bus_RdAck                   : out std_logic;
130
    IP2Bus_WrAck                   : out std_logic;
131
    IP2Bus_Error                   : out std_logic;
132
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
133
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
134
  );
135
 
136
  attribute SIGIS : string;
137
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
138
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
139
 
140
end entity user_logic;
141
 
142
------------------------------------------------------------------------------
143
-- Architecture section
144
------------------------------------------------------------------------------
145
 
146
architecture IMP of user_logic is
147
 
148
  --USER signal declarations added here, as needed for user logic
149
 
150
  ------------------------------------------------------------------
151
  -- Signals for multiplier core slave model s/w accessible register
152
  ------------------------------------------------------------------
153
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
154
  signal slv_reg_write_sel              : std_logic_vector(0 to 0);
155
  signal slv_reg_read_sel               : std_logic_vector(0 to 0);
156
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
157
  signal slv_read_ack                   : std_logic;
158
  signal slv_write_ack                  : std_logic;
159
 
160
  signal load_flags                     : std_logic;
161
 
162
  ------------------------------------------------------------------
163
  -- Signals for multiplier core interrupt
164
  ------------------------------------------------------------------
165
  signal core_interrupt                 : std_logic_vector(0 to 0);
166
  signal core_fifo_full                : std_logic;
167
  signal core_fifo_nopush               : std_logic;
168
  signal core_ready                     : std_logic;
169
  signal core_mem_collision             : std_logic;
170
 
171
  ------------------------------------------------------------------
172
  -- Signals for multiplier core control
173
  ------------------------------------------------------------------
174
  signal core_start                     : std_logic;
175
  signal core_run_auto                  : std_logic;
176
  signal core_p_sel                     : std_logic_vector(1 downto 0);
177
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
178
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
179
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
180
  signal core_flags                     : std_logic_vector(15 downto 0);
181
 
182
  ------------------------------------------------------------------
183
  -- Signals for multiplier core memory space
184
  ------------------------------------------------------------------
185
  signal mem_address                    : std_logic_vector(0 to 5);
186
  signal mem_select                     : std_logic_vector(0 to 5);
187
  signal mem_read_enable                : std_logic;
188
  signal mem_read_enable_dly1           : std_logic;
189
  signal mem_read_req                   : std_logic;
190
  signal mem_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
191
  signal mem_read_ack_dly1              : std_logic;
192
  signal mem_read_ack                   : std_logic;
193
  signal mem_write_ack                  : std_logic;
194
 
195
  signal core_rw_address                : std_logic_vector (8 downto 0);
196
  signal core_data_in                   : std_logic_vector(31 downto 0);
197
  signal core_fifo_din                  : std_logic_vector(31 downto 0);
198
  signal sel_mno                        : std_logic;
199
  signal sel_op                         : std_logic_vector(1 downto 0);
200
  signal core_data_out                  : std_logic_vector(31 downto 0);
201
  signal core_write_enable              : std_logic;
202
  signal core_fifo_push                 : std_logic;
203
begin
204
 
205
  --USER logic implementation added here
206
  --ctrl_sigs <= 
207
 
208
  ------------------------------------------
209
  -- Example code to read/write user logic slave model s/w accessible registers
210
  -- 
211
  -- Note:
212
  -- The example code presented here is to show you one way of reading/writing
213
  -- software accessible registers implemented in the user logic slave model.
214
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
215
  -- to one software accessible register by the top level template. For example,
216
  -- if you have four 32 bit software accessible registers in the user logic,
217
  -- you are basically operating on the following memory mapped registers:
218
  -- 
219
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
220
  --                     "1000"   C_BASEADDR + 0x0
221
  --                     "0100"   C_BASEADDR + 0x4
222
  --                     "0010"   C_BASEADDR + 0x8
223
  --                     "0001"   C_BASEADDR + 0xC
224
  -- 
225
  ------------------------------------------
226
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
227
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
228
  slv_write_ack     <= Bus2IP_WrCE(0);
229
  slv_read_ack      <= Bus2IP_RdCE(0);
230
 
231
  -- implement slave model software accessible register(s)
232
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
233
  begin
234
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
235
      if Bus2IP_Reset = '1' then
236
        slv_reg0 <= (others => '0');
237
      elsif load_flags = '1' then
238
                  slv_reg0 <= slv_reg0(0 to 15) & core_flags;
239
                else
240
        case slv_reg_write_sel is
241
          when "1" =>
242
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
243
              if ( Bus2IP_BE(byte_index) = '1' ) then
244
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
245
              end if;
246
            end loop;
247
          when others => null;
248
        end case;
249
      end if;
250
    end if;
251
 
252
  end process SLAVE_REG_WRITE_PROC;
253
 
254
  -- implement slave model software accessible register(s) read mux
255
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
256
  begin
257
 
258
    case slv_reg_read_sel is
259
      when "1" => slv_ip2bus_data <= slv_reg0;
260
      when others => slv_ip2bus_data <= (others => '0');
261
    end case;
262
 
263
  end process SLAVE_REG_READ_PROC;
264
 
265
  ------------------------------------------
266
  -- Multiplier core interrupts form IP core interrupt
267
  ------------------------------------------
268
 
269
  core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
270
  IP2Bus_IntrEvent <= core_interrupt;
271
 
272
  FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
273
  begin
274
    if Bus2IP_Reset = '1' then
275
           core_flags <= (others => '0');
276
                load_flags <= '0';
277
    elsif rising_edge(Bus2IP_Clk) then
278
           if core_start = '1' then
279
                  core_flags <= (others => '0');
280
                else
281
                  if core_ready = '1' then
282
                    core_flags(15) <= '1';
283
                  else
284
                    core_flags(15) <= core_flags(15);
285
                  end if;
286
                  if core_mem_collision = '1' then
287
                    core_flags(14) <= '1';
288
                  else
289
                    core_flags(14) <= core_flags(14);
290
                  end if;
291
                  if core_fifo_full = '1' then
292
                         core_flags(13) <= '1';
293
                  else
294
                    core_flags(13) <= core_flags(13);
295
                  end if;
296
                  if core_fifo_nopush = '1' then
297
                         core_flags(12) <= '1';
298
                  else
299
                    core_flags(12) <= core_flags(12);
300
                  end if;
301
                end if;
302
                --
303
                load_flags <= core_interrupt(0);
304
         end if;
305
  end process FLAGS_CNTRL_PROC;
306
 
307
  ------------------------------------------
308
  -- Example code to access user logic memory region
309
  -- 
310
  -- Note:
311
  -- The example code presented here is to show you one way of using
312
  -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
313
  -- and Bus2IP_RNW IPIC signals are dedicated to these user logic
314
  -- memory spaces. Each user logic memory space has its own address
315
  -- range and is allocated one bit on the Bus2IP_CS signal to indicated
316
  -- selection of that memory space. Typically these user logic memory
317
  -- spaces are used to implement memory controller type cores, but it
318
  -- can also be used in cores that need to access additional address space
319
  -- (non C_BASEADDR based), s.t. bridges. This code snippet infers
320
  -- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
321
  ------------------------------------------
322
  mem_select      <= Bus2IP_CS;
323
  mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
324
  mem_read_ack    <= mem_read_ack_dly1;
325
  mem_write_ack   <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
326
  mem_address     <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
327
 
328
  -- implement single clock wide read request
329
  mem_read_req    <= mem_read_enable and not(mem_read_enable_dly1);
330
  BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
331
  begin
332
 
333
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
334
      if ( Bus2IP_Reset = '1' ) then
335
        mem_read_enable_dly1 <= '0';
336
      else
337
        mem_read_enable_dly1 <= mem_read_enable;
338
      end if;
339
    end if;
340
 
341
  end process BRAM_RD_REQ_PROC;
342
 
343
  -- this process generates the read acknowledge 1 clock after read enable
344
  -- is presented to the BRAM block. The BRAM block has a 1 clock delay
345
  -- from read enable to data out.
346
  BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
347
  begin
348
 
349
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
350
      if ( Bus2IP_Reset = '1' ) then
351
        mem_read_ack_dly1 <= '0';
352
      else
353
        mem_read_ack_dly1 <= mem_read_req;
354
      end if;
355
    end if;
356
 
357
  end process BRAM_RD_ACK_PROC;
358
 
359
    -- address logic
360
  Sel_MNO <= mem_select(0);
361
  with mem_select(1 to 4) select
362
    Sel_Op <= "00" when "1000",
363
                   "01" when "0100",
364
                                  "10" when "0010",
365
                                  "11" when others;
366
 
367
 
368
  core_rw_address <= Sel_MNO & Sel_Op & mem_address;
369
 
370
  -- data-in
371
  core_data_in <= Bus2IP_Data;
372
  core_fifo_din <= Bus2IP_Data;
373
  core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
374
  core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
375
  -- no read mux required, we can only read from core_data_out
376
  mem_ip2bus_data <= core_data_out;
377
 
378
  ------------------------------------------
379
  -- Map slv_reg0 bits to core control signals 
380
  ------------------------------------------
381
  core_start <= slv_reg0(8);
382
  core_run_auto <= slv_reg0(9);
383
  core_p_sel <= slv_reg0(0 to 1);
384
  core_dest_op_single <= slv_reg0(2 to 3);
385
  core_x_sel_single <= slv_reg0(4 to 5);
386
  core_y_sel_single <= slv_reg0(6 to 7);
387
 
388
  ------------------------------------------
389
  -- Multiplier core instance
390
  ------------------------------------------
391 40 JonasDC
  the_multiplier: mod_sim_exp_core
392 2 JonasDC
  port map(        clk => Bus2IP_Clk, -- v
393
                      reset => Bus2IP_Reset, -- v
394
                        -- operand memory interface (plb shared memory)
395
                         write_enable => core_write_enable,
396
               data_in => core_data_in,
397
            rw_address => core_rw_address,
398
              data_out => core_data_out,
399
                                 collision => core_mem_collision, -- v
400
                        -- op_sel fifo interface
401
                             fifo_din => core_fifo_din,
402
                            fifo_push => core_fifo_push,
403
                            fifo_full => core_fifo_full, -- v
404
                          fifo_nopush => core_fifo_nopush, -- v
405
                        -- ctrl signals
406
                                start => core_start, -- v
407
                             run_auto => core_run_auto, -- v
408
                                ready => core_ready, -- v
409
                    x_sel_single => core_x_sel_single, -- v
410
                    y_sel_single => core_y_sel_single, -- v
411
                  dest_op_single => core_dest_op_single, -- v
412
                 p_sel => core_p_sel, -- v
413
                                 calc_time => calc_time -- v
414
  );
415
 
416
  ------------------------------------------
417
  -- Drive IP to Bus signals
418
  ------------------------------------------
419
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
420
                  mem_ip2bus_data when mem_read_ack = '1' else
421
                  (others => '0');
422
 
423
  IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
424
  IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
425
  IP2Bus_Error <= '0';
426
 
427
end IMP;

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