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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Blame information for rev 65

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1 2 JonasDC
------------------------------------------------------------------------------
2
-- user_logic.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
--
5
-- ***************************************************************************
6
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
7
-- **                                                                       **
8
-- ** Xilinx, Inc.                                                          **
9
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
10
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
11
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
12
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
13
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
14
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
15
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
16
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
17
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
18
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
19
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
20
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
21
-- ** FOR A PARTICULAR PURPOSE.                                             **
22
-- **                                                                       **
23
-- ***************************************************************************
24
--
25
------------------------------------------------------------------------------
26
-- Filename:          user_logic.vhd
27
-- Version:           2.00.a
28
-- Description:       User logic.
29
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
30
-- VHDL Standard:     VHDL'93
31
------------------------------------------------------------------------------
32
-- Naming Conventions:
33
--   active low signals:                    "*_n"
34
--   clock signals:                         "clk", "clk_div#", "clk_#x"
35
--   reset signals:                         "rst", "rst_n"
36
--   generics:                              "C_*"
37
--   user defined types:                    "*_TYPE"
38
--   state machine next state:              "*_ns"
39
--   state machine current state:           "*_cs"
40
--   combinatorial signals:                 "*_com"
41
--   pipelined or register delay signals:   "*_d#"
42
--   counter signals:                       "*cnt*"
43
--   clock enable signals:                  "*_ce"
44
--   internal version of output port:       "*_i"
45
--   device pins:                           "*_pin"
46
--   ports:                                 "- Names begin with Uppercase"
47
--   processes:                             "*_PROCESS"
48
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
49
------------------------------------------------------------------------------
50
 
51
-- DO NOT EDIT BELOW THIS LINE --------------------
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_arith.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library proc_common_v3_00_a;
58
use proc_common_v3_00_a.proc_common_pkg.all;
59
 
60
-- DO NOT EDIT ABOVE THIS LINE --------------------
61
 
62
--USER libraries added here
63 40 JonasDC
library mod_sim_exp;
64 42 JonasDC
use mod_sim_exp.mod_sim_exp_pkg.all;
65 2 JonasDC
 
66
------------------------------------------------------------------------------
67
-- Entity section
68
------------------------------------------------------------------------------
69
-- Definition of Generics:
70
--   C_SLV_AWIDTH                 -- Slave interface address bus width
71
--   C_SLV_DWIDTH                 -- Slave interface data bus width
72
--   C_NUM_REG                    -- Number of software accessible registers
73
--   C_NUM_MEM                    -- Number of memory spaces
74
--   C_NUM_INTR                   -- Number of interrupt event
75
--
76
-- Definition of Ports:
77
--   Bus2IP_Clk                   -- Bus to IP clock
78
--   Bus2IP_Reset                 -- Bus to IP reset
79
--   Bus2IP_Addr                  -- Bus to IP address bus
80
--   Bus2IP_CS                    -- Bus to IP chip select for user logic memory selection
81
--   Bus2IP_RNW                   -- Bus to IP read/not write
82
--   Bus2IP_Data                  -- Bus to IP data bus
83
--   Bus2IP_BE                    -- Bus to IP byte enables
84
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
85
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
86
--   IP2Bus_Data                  -- IP to Bus data bus
87
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
88
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
89
--   IP2Bus_Error                 -- IP to Bus error response
90
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
91
------------------------------------------------------------------------------
92
 
93
entity user_logic is
94
  generic
95
  (
96
    -- ADD USER GENERICS BELOW THIS LINE ---------------
97
    --USER generics added here
98 43 JonasDC
    -- Multiplier parameters
99
    C_NR_BITS_TOTAL   : integer := 1536;
100
    C_NR_STAGES_TOTAL : integer := 96;
101
    C_NR_STAGES_LOW   : integer := 32;
102
    C_SPLIT_PIPELINE  : boolean := true;
103 65 JonasDC
    C_FIFO_DEPTH      : integer := 32;
104 2 JonasDC
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
105
 
106
    -- DO NOT EDIT BELOW THIS LINE ---------------------
107
    -- Bus protocol parameters, do not add to or delete
108
    C_SLV_AWIDTH                   : integer              := 32;
109
    C_SLV_DWIDTH                   : integer              := 32;
110
    C_NUM_REG                      : integer              := 1;
111
    C_NUM_MEM                      : integer              := 6;
112
    C_NUM_INTR                     : integer              := 1
113
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
114
  );
115
  port
116
  (
117
    -- ADD USER PORTS BELOW THIS LINE ------------------
118
    --USER ports added here
119
         calc_time                      : out std_logic;
120
        -- ctrl_sigs                      : out std_logic_vector( downto );
121
    -- ADD USER PORTS ABOVE THIS LINE ------------------
122
 
123
    -- DO NOT EDIT BELOW THIS LINE ---------------------
124
    -- Bus protocol ports, do not add to or delete
125
    Bus2IP_Clk                     : in  std_logic;
126
    Bus2IP_Reset                   : in  std_logic;
127
    Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
128
    Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
129
    Bus2IP_RNW                     : in  std_logic;
130
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
131
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
132
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
133
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
134
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
135
    IP2Bus_RdAck                   : out std_logic;
136
    IP2Bus_WrAck                   : out std_logic;
137
    IP2Bus_Error                   : out std_logic;
138
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
139
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
140
  );
141
 
142
  attribute SIGIS : string;
143
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
144
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
145
 
146
end entity user_logic;
147
 
148
------------------------------------------------------------------------------
149
-- Architecture section
150
------------------------------------------------------------------------------
151
 
152
architecture IMP of user_logic is
153
 
154
  --USER signal declarations added here, as needed for user logic
155
 
156
  ------------------------------------------------------------------
157
  -- Signals for multiplier core slave model s/w accessible register
158
  ------------------------------------------------------------------
159
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
160
  signal slv_reg_write_sel              : std_logic_vector(0 to 0);
161
  signal slv_reg_read_sel               : std_logic_vector(0 to 0);
162
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
163
  signal slv_read_ack                   : std_logic;
164
  signal slv_write_ack                  : std_logic;
165
 
166
  signal load_flags                     : std_logic;
167
 
168
  ------------------------------------------------------------------
169
  -- Signals for multiplier core interrupt
170
  ------------------------------------------------------------------
171
  signal core_interrupt                 : std_logic_vector(0 to 0);
172 45 JonasDC
  signal core_fifo_full                 : std_logic;
173 2 JonasDC
  signal core_fifo_nopush               : std_logic;
174
  signal core_ready                     : std_logic;
175
  signal core_mem_collision             : std_logic;
176
 
177
  ------------------------------------------------------------------
178
  -- Signals for multiplier core control
179
  ------------------------------------------------------------------
180
  signal core_start                     : std_logic;
181 45 JonasDC
  signal core_exp_m                     : std_logic;
182 2 JonasDC
  signal core_p_sel                     : std_logic_vector(1 downto 0);
183
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
184
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
185
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
186
  signal core_flags                     : std_logic_vector(15 downto 0);
187 65 JonasDC
  signal core_modulus_sel               : std_logic_vector(0 downto 0);
188 2 JonasDC
 
189
  ------------------------------------------------------------------
190
  -- Signals for multiplier core memory space
191
  ------------------------------------------------------------------
192
  signal mem_address                    : std_logic_vector(0 to 5);
193
  signal mem_select                     : std_logic_vector(0 to 5);
194
  signal mem_read_enable                : std_logic;
195
  signal mem_read_enable_dly1           : std_logic;
196
  signal mem_read_req                   : std_logic;
197
  signal mem_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
198
  signal mem_read_ack_dly1              : std_logic;
199
  signal mem_read_ack                   : std_logic;
200
  signal mem_write_ack                  : std_logic;
201
 
202
  signal core_rw_address                : std_logic_vector (8 downto 0);
203
  signal core_data_in                   : std_logic_vector(31 downto 0);
204
  signal core_fifo_din                  : std_logic_vector(31 downto 0);
205
  signal sel_mno                        : std_logic;
206
  signal sel_op                         : std_logic_vector(1 downto 0);
207
  signal core_data_out                  : std_logic_vector(31 downto 0);
208
  signal core_write_enable              : std_logic;
209
  signal core_fifo_push                 : std_logic;
210
begin
211
 
212
  --USER logic implementation added here
213
  --ctrl_sigs <= 
214
 
215
  ------------------------------------------
216
  -- Example code to read/write user logic slave model s/w accessible registers
217
  -- 
218
  -- Note:
219
  -- The example code presented here is to show you one way of reading/writing
220
  -- software accessible registers implemented in the user logic slave model.
221
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
222
  -- to one software accessible register by the top level template. For example,
223
  -- if you have four 32 bit software accessible registers in the user logic,
224
  -- you are basically operating on the following memory mapped registers:
225
  -- 
226
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
227
  --                     "1000"   C_BASEADDR + 0x0
228
  --                     "0100"   C_BASEADDR + 0x4
229
  --                     "0010"   C_BASEADDR + 0x8
230
  --                     "0001"   C_BASEADDR + 0xC
231
  -- 
232
  ------------------------------------------
233
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
234
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
235
  slv_write_ack     <= Bus2IP_WrCE(0);
236
  slv_read_ack      <= Bus2IP_RdCE(0);
237
 
238
  -- implement slave model software accessible register(s)
239
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
240
  begin
241
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
242
      if Bus2IP_Reset = '1' then
243
        slv_reg0 <= (others => '0');
244
      elsif load_flags = '1' then
245
                  slv_reg0 <= slv_reg0(0 to 15) & core_flags;
246
                else
247
        case slv_reg_write_sel is
248
          when "1" =>
249
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
250
              if ( Bus2IP_BE(byte_index) = '1' ) then
251
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
252
              end if;
253
            end loop;
254
          when others => null;
255
        end case;
256
      end if;
257
    end if;
258
 
259
  end process SLAVE_REG_WRITE_PROC;
260
 
261
  -- implement slave model software accessible register(s) read mux
262
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
263
  begin
264
 
265
    case slv_reg_read_sel is
266
      when "1" => slv_ip2bus_data <= slv_reg0;
267
      when others => slv_ip2bus_data <= (others => '0');
268
    end case;
269
 
270
  end process SLAVE_REG_READ_PROC;
271
 
272
  ------------------------------------------
273
  -- Multiplier core interrupts form IP core interrupt
274
  ------------------------------------------
275
 
276
  core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
277
  IP2Bus_IntrEvent <= core_interrupt;
278
 
279
  FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
280
  begin
281
    if Bus2IP_Reset = '1' then
282
           core_flags <= (others => '0');
283
                load_flags <= '0';
284
    elsif rising_edge(Bus2IP_Clk) then
285
           if core_start = '1' then
286
                  core_flags <= (others => '0');
287
                else
288
                  if core_ready = '1' then
289
                    core_flags(15) <= '1';
290
                  else
291
                    core_flags(15) <= core_flags(15);
292
                  end if;
293
                  if core_mem_collision = '1' then
294
                    core_flags(14) <= '1';
295
                  else
296
                    core_flags(14) <= core_flags(14);
297
                  end if;
298
                  if core_fifo_full = '1' then
299
                         core_flags(13) <= '1';
300
                  else
301
                    core_flags(13) <= core_flags(13);
302
                  end if;
303
                  if core_fifo_nopush = '1' then
304
                         core_flags(12) <= '1';
305
                  else
306
                    core_flags(12) <= core_flags(12);
307
                  end if;
308
                end if;
309
                --
310
                load_flags <= core_interrupt(0);
311
         end if;
312
  end process FLAGS_CNTRL_PROC;
313
 
314
  ------------------------------------------
315
  -- Example code to access user logic memory region
316
  -- 
317
  -- Note:
318
  -- The example code presented here is to show you one way of using
319
  -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
320
  -- and Bus2IP_RNW IPIC signals are dedicated to these user logic
321
  -- memory spaces. Each user logic memory space has its own address
322
  -- range and is allocated one bit on the Bus2IP_CS signal to indicated
323
  -- selection of that memory space. Typically these user logic memory
324
  -- spaces are used to implement memory controller type cores, but it
325
  -- can also be used in cores that need to access additional address space
326
  -- (non C_BASEADDR based), s.t. bridges. This code snippet infers
327
  -- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
328
  ------------------------------------------
329
  mem_select      <= Bus2IP_CS;
330
  mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
331
  mem_read_ack    <= mem_read_ack_dly1;
332
  mem_write_ack   <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
333
  mem_address     <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
334
 
335
  -- implement single clock wide read request
336
  mem_read_req    <= mem_read_enable and not(mem_read_enable_dly1);
337
  BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
338
  begin
339
 
340
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
341
      if ( Bus2IP_Reset = '1' ) then
342
        mem_read_enable_dly1 <= '0';
343 42 JonasDC
 
344 2 JonasDC
      else
345
        mem_read_enable_dly1 <= mem_read_enable;
346
      end if;
347
    end if;
348
 
349
  end process BRAM_RD_REQ_PROC;
350
 
351
  -- this process generates the read acknowledge 1 clock after read enable
352
  -- is presented to the BRAM block. The BRAM block has a 1 clock delay
353
  -- from read enable to data out.
354
  BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
355
  begin
356
 
357
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
358
      if ( Bus2IP_Reset = '1' ) then
359
        mem_read_ack_dly1 <= '0';
360
      else
361
        mem_read_ack_dly1 <= mem_read_req;
362
      end if;
363
    end if;
364
 
365
  end process BRAM_RD_ACK_PROC;
366
 
367
    -- address logic
368
  Sel_MNO <= mem_select(0);
369
  with mem_select(1 to 4) select
370
    Sel_Op <= "00" when "1000",
371
                   "01" when "0100",
372
                                  "10" when "0010",
373
                                  "11" when others;
374
 
375
 
376
  core_rw_address <= Sel_MNO & Sel_Op & mem_address;
377
 
378
  -- data-in
379
  core_data_in <= Bus2IP_Data;
380
  core_fifo_din <= Bus2IP_Data;
381
  core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
382
  core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
383
  -- no read mux required, we can only read from core_data_out
384
  mem_ip2bus_data <= core_data_out;
385
 
386
  ------------------------------------------
387
  -- Map slv_reg0 bits to core control signals 
388
  ------------------------------------------
389 65 JonasDC
 
390 2 JonasDC
  core_p_sel <= slv_reg0(0 to 1);
391
  core_dest_op_single <= slv_reg0(2 to 3);
392
  core_x_sel_single <= slv_reg0(4 to 5);
393
  core_y_sel_single <= slv_reg0(6 to 7);
394 65 JonasDC
  core_start <= slv_reg0(8);
395
  core_exp_m <= slv_reg0(9);
396
  core_modulus_sel <= slv_reg0(10 to 10);
397 2 JonasDC
 
398
  ------------------------------------------
399
  -- Multiplier core instance
400
  ------------------------------------------
401 40 JonasDC
  the_multiplier: mod_sim_exp_core
402 43 JonasDC
  generic map(
403
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
404
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
405
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
406 65 JonasDC
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
407
    C_NR_OP           => 4,
408
    C_NR_M            => 2,
409
    C_FIFO_DEPTH      => C_FIFO_DEPTH
410 43 JonasDC
  )
411
  port map(
412
    clk   => Bus2IP_Clk,
413
    reset => Bus2IP_Reset,
414
      -- operand memory interface (plb shared memory)
415
    write_enable => core_write_enable,
416
    data_in      => core_data_in,
417
    rw_address   => core_rw_address,
418
    data_out     => core_data_out,
419
    collision    => core_mem_collision,
420
      -- op_sel fifo interface
421
    fifo_din    => core_fifo_din,
422
    fifo_push   => core_fifo_push,
423
    fifo_full   => core_fifo_full,
424
    fifo_nopush => core_fifo_nopush,
425
      -- ctrl signals
426
    start          => core_start,
427 45 JonasDC
    exp_m          => core_exp_m,
428 43 JonasDC
    ready          => core_ready,
429
    x_sel_single   => core_x_sel_single,
430
    y_sel_single   => core_y_sel_single,
431
    dest_op_single => core_dest_op_single,
432
    p_sel          => core_p_sel,
433 65 JonasDC
    calc_time      => calc_time,
434
    modulus_sel    => core_modulus_sel
435 2 JonasDC
  );
436
 
437 43 JonasDC
 
438 2 JonasDC
  ------------------------------------------
439
  -- Drive IP to Bus signals
440
  ------------------------------------------
441
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
442
                  mem_ip2bus_data when mem_read_ack = '1' else
443
                  (others => '0');
444
 
445
  IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
446
  IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
447
  IP2Bus_Error <= '0';
448
 
449
end IMP;

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