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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Blame information for rev 84

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1 2 JonasDC
------------------------------------------------------------------------------
2
-- user_logic.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
--
5
-- ***************************************************************************
6
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
7
-- **                                                                       **
8
-- ** Xilinx, Inc.                                                          **
9
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
10
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
11
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
12
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
13
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
14
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
15
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
16
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
17
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
18
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
19
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
20
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
21
-- ** FOR A PARTICULAR PURPOSE.                                             **
22
-- **                                                                       **
23
-- ***************************************************************************
24
--
25
------------------------------------------------------------------------------
26
-- Filename:          user_logic.vhd
27
-- Version:           2.00.a
28
-- Description:       User logic.
29
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
30
-- VHDL Standard:     VHDL'93
31
------------------------------------------------------------------------------
32
-- Naming Conventions:
33
--   active low signals:                    "*_n"
34
--   clock signals:                         "clk", "clk_div#", "clk_#x"
35
--   reset signals:                         "rst", "rst_n"
36
--   generics:                              "C_*"
37
--   user defined types:                    "*_TYPE"
38
--   state machine next state:              "*_ns"
39
--   state machine current state:           "*_cs"
40
--   combinatorial signals:                 "*_com"
41
--   pipelined or register delay signals:   "*_d#"
42
--   counter signals:                       "*cnt*"
43
--   clock enable signals:                  "*_ce"
44
--   internal version of output port:       "*_i"
45
--   device pins:                           "*_pin"
46
--   ports:                                 "- Names begin with Uppercase"
47
--   processes:                             "*_PROCESS"
48
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
49
------------------------------------------------------------------------------
50
 
51
-- DO NOT EDIT BELOW THIS LINE --------------------
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_arith.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library proc_common_v3_00_a;
58
use proc_common_v3_00_a.proc_common_pkg.all;
59
 
60
-- DO NOT EDIT ABOVE THIS LINE --------------------
61
 
62
--USER libraries added here
63 40 JonasDC
library mod_sim_exp;
64 42 JonasDC
use mod_sim_exp.mod_sim_exp_pkg.all;
65 2 JonasDC
 
66
------------------------------------------------------------------------------
67
-- Entity section
68
------------------------------------------------------------------------------
69
-- Definition of Generics:
70
--   C_SLV_AWIDTH                 -- Slave interface address bus width
71
--   C_SLV_DWIDTH                 -- Slave interface data bus width
72
--   C_NUM_REG                    -- Number of software accessible registers
73
--   C_NUM_MEM                    -- Number of memory spaces
74
--   C_NUM_INTR                   -- Number of interrupt event
75
--
76
-- Definition of Ports:
77
--   Bus2IP_Clk                   -- Bus to IP clock
78
--   Bus2IP_Reset                 -- Bus to IP reset
79
--   Bus2IP_Addr                  -- Bus to IP address bus
80
--   Bus2IP_CS                    -- Bus to IP chip select for user logic memory selection
81
--   Bus2IP_RNW                   -- Bus to IP read/not write
82
--   Bus2IP_Data                  -- Bus to IP data bus
83
--   Bus2IP_BE                    -- Bus to IP byte enables
84
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
85
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
86
--   IP2Bus_Data                  -- IP to Bus data bus
87
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
88
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
89
--   IP2Bus_Error                 -- IP to Bus error response
90
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
91
------------------------------------------------------------------------------
92
 
93
entity user_logic is
94
  generic
95
  (
96
    -- ADD USER GENERICS BELOW THIS LINE ---------------
97
    --USER generics added here
98 43 JonasDC
    -- Multiplier parameters
99
    C_NR_BITS_TOTAL   : integer := 1536;
100
    C_NR_STAGES_TOTAL : integer := 96;
101
    C_NR_STAGES_LOW   : integer := 32;
102
    C_SPLIT_PIPELINE  : boolean := true;
103 65 JonasDC
    C_FIFO_DEPTH      : integer := 32;
104 73 JonasDC
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
105 84 JonasDC
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
106 2 JonasDC
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
107
 
108
    -- DO NOT EDIT BELOW THIS LINE ---------------------
109
    -- Bus protocol parameters, do not add to or delete
110
    C_SLV_AWIDTH                   : integer              := 32;
111
    C_SLV_DWIDTH                   : integer              := 32;
112
    C_NUM_REG                      : integer              := 1;
113
    C_NUM_MEM                      : integer              := 6;
114
    C_NUM_INTR                     : integer              := 1
115
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
116
  );
117
  port
118
  (
119
    -- ADD USER PORTS BELOW THIS LINE ------------------
120
    --USER ports added here
121
         calc_time                      : out std_logic;
122
        -- ctrl_sigs                      : out std_logic_vector( downto );
123
    -- ADD USER PORTS ABOVE THIS LINE ------------------
124
 
125
    -- DO NOT EDIT BELOW THIS LINE ---------------------
126
    -- Bus protocol ports, do not add to or delete
127
    Bus2IP_Clk                     : in  std_logic;
128
    Bus2IP_Reset                   : in  std_logic;
129
    Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
130
    Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
131
    Bus2IP_RNW                     : in  std_logic;
132
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
133
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
134
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
135
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
136
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
137
    IP2Bus_RdAck                   : out std_logic;
138
    IP2Bus_WrAck                   : out std_logic;
139
    IP2Bus_Error                   : out std_logic;
140
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
141
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
142
  );
143
 
144
  attribute SIGIS : string;
145
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
146
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
147
 
148
end entity user_logic;
149
 
150
------------------------------------------------------------------------------
151
-- Architecture section
152
------------------------------------------------------------------------------
153
 
154
architecture IMP of user_logic is
155
 
156
  --USER signal declarations added here, as needed for user logic
157
 
158
  ------------------------------------------------------------------
159
  -- Signals for multiplier core slave model s/w accessible register
160
  ------------------------------------------------------------------
161
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
162
  signal slv_reg_write_sel              : std_logic_vector(0 to 0);
163
  signal slv_reg_read_sel               : std_logic_vector(0 to 0);
164
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
165
  signal slv_read_ack                   : std_logic;
166
  signal slv_write_ack                  : std_logic;
167
 
168
  signal load_flags                     : std_logic;
169
 
170
  ------------------------------------------------------------------
171
  -- Signals for multiplier core interrupt
172
  ------------------------------------------------------------------
173
  signal core_interrupt                 : std_logic_vector(0 to 0);
174 45 JonasDC
  signal core_fifo_full                 : std_logic;
175 2 JonasDC
  signal core_fifo_nopush               : std_logic;
176
  signal core_ready                     : std_logic;
177
  signal core_mem_collision             : std_logic;
178
 
179
  ------------------------------------------------------------------
180
  -- Signals for multiplier core control
181
  ------------------------------------------------------------------
182
  signal core_start                     : std_logic;
183 45 JonasDC
  signal core_exp_m                     : std_logic;
184 2 JonasDC
  signal core_p_sel                     : std_logic_vector(1 downto 0);
185
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
186
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
187
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
188
  signal core_flags                     : std_logic_vector(15 downto 0);
189 77 JonasDC
  signal core_modulus_sel               : std_logic;
190 2 JonasDC
 
191
  ------------------------------------------------------------------
192
  -- Signals for multiplier core memory space
193
  ------------------------------------------------------------------
194
  signal mem_address                    : std_logic_vector(0 to 5);
195
  signal mem_select                     : std_logic_vector(0 to 5);
196
  signal mem_read_enable                : std_logic;
197
  signal mem_read_enable_dly1           : std_logic;
198
  signal mem_read_req                   : std_logic;
199
  signal mem_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
200
  signal mem_read_ack_dly1              : std_logic;
201
  signal mem_read_ack                   : std_logic;
202
  signal mem_write_ack                  : std_logic;
203
 
204
  signal core_rw_address                : std_logic_vector (8 downto 0);
205
  signal core_data_in                   : std_logic_vector(31 downto 0);
206
  signal core_fifo_din                  : std_logic_vector(31 downto 0);
207
  signal sel_mno                        : std_logic;
208
  signal sel_op                         : std_logic_vector(1 downto 0);
209
  signal core_data_out                  : std_logic_vector(31 downto 0);
210
  signal core_write_enable              : std_logic;
211
  signal core_fifo_push                 : std_logic;
212
begin
213
 
214
  --USER logic implementation added here
215
  --ctrl_sigs <= 
216
 
217
  ------------------------------------------
218
  -- Example code to read/write user logic slave model s/w accessible registers
219
  -- 
220
  -- Note:
221
  -- The example code presented here is to show you one way of reading/writing
222
  -- software accessible registers implemented in the user logic slave model.
223
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
224
  -- to one software accessible register by the top level template. For example,
225
  -- if you have four 32 bit software accessible registers in the user logic,
226
  -- you are basically operating on the following memory mapped registers:
227
  -- 
228
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
229
  --                     "1000"   C_BASEADDR + 0x0
230
  --                     "0100"   C_BASEADDR + 0x4
231
  --                     "0010"   C_BASEADDR + 0x8
232
  --                     "0001"   C_BASEADDR + 0xC
233
  -- 
234
  ------------------------------------------
235
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
236
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
237
  slv_write_ack     <= Bus2IP_WrCE(0);
238
  slv_read_ack      <= Bus2IP_RdCE(0);
239
 
240
  -- implement slave model software accessible register(s)
241
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
242
  begin
243
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
244
      if Bus2IP_Reset = '1' then
245
        slv_reg0 <= (others => '0');
246
      elsif load_flags = '1' then
247
                  slv_reg0 <= slv_reg0(0 to 15) & core_flags;
248
                else
249
        case slv_reg_write_sel is
250
          when "1" =>
251
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
252
              if ( Bus2IP_BE(byte_index) = '1' ) then
253
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
254
              end if;
255
            end loop;
256
          when others => null;
257
        end case;
258
      end if;
259
    end if;
260
 
261
  end process SLAVE_REG_WRITE_PROC;
262
 
263
  -- implement slave model software accessible register(s) read mux
264
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
265
  begin
266
 
267
    case slv_reg_read_sel is
268
      when "1" => slv_ip2bus_data <= slv_reg0;
269
      when others => slv_ip2bus_data <= (others => '0');
270
    end case;
271
 
272
  end process SLAVE_REG_READ_PROC;
273
 
274
  ------------------------------------------
275
  -- Multiplier core interrupts form IP core interrupt
276
  ------------------------------------------
277
 
278
  core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
279
  IP2Bus_IntrEvent <= core_interrupt;
280
 
281
  FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
282
  begin
283
    if Bus2IP_Reset = '1' then
284
           core_flags <= (others => '0');
285
                load_flags <= '0';
286
    elsif rising_edge(Bus2IP_Clk) then
287
           if core_start = '1' then
288
                  core_flags <= (others => '0');
289
                else
290
                  if core_ready = '1' then
291
                    core_flags(15) <= '1';
292
                  else
293
                    core_flags(15) <= core_flags(15);
294
                  end if;
295
                  if core_mem_collision = '1' then
296
                    core_flags(14) <= '1';
297
                  else
298
                    core_flags(14) <= core_flags(14);
299
                  end if;
300
                  if core_fifo_full = '1' then
301
                         core_flags(13) <= '1';
302
                  else
303
                    core_flags(13) <= core_flags(13);
304
                  end if;
305
                  if core_fifo_nopush = '1' then
306
                         core_flags(12) <= '1';
307
                  else
308
                    core_flags(12) <= core_flags(12);
309
                  end if;
310
                end if;
311
                --
312
                load_flags <= core_interrupt(0);
313
         end if;
314
  end process FLAGS_CNTRL_PROC;
315
 
316
  ------------------------------------------
317
  -- Example code to access user logic memory region
318
  -- 
319
  -- Note:
320
  -- The example code presented here is to show you one way of using
321
  -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
322
  -- and Bus2IP_RNW IPIC signals are dedicated to these user logic
323
  -- memory spaces. Each user logic memory space has its own address
324
  -- range and is allocated one bit on the Bus2IP_CS signal to indicated
325
  -- selection of that memory space. Typically these user logic memory
326
  -- spaces are used to implement memory controller type cores, but it
327
  -- can also be used in cores that need to access additional address space
328
  -- (non C_BASEADDR based), s.t. bridges. This code snippet infers
329
  -- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
330
  ------------------------------------------
331
  mem_select      <= Bus2IP_CS;
332
  mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
333
  mem_read_ack    <= mem_read_ack_dly1;
334
  mem_write_ack   <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
335
  mem_address     <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
336
 
337
  -- implement single clock wide read request
338
  mem_read_req    <= mem_read_enable and not(mem_read_enable_dly1);
339
  BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
340
  begin
341
 
342
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
343
      if ( Bus2IP_Reset = '1' ) then
344
        mem_read_enable_dly1 <= '0';
345 42 JonasDC
 
346 2 JonasDC
      else
347
        mem_read_enable_dly1 <= mem_read_enable;
348
      end if;
349
    end if;
350
 
351
  end process BRAM_RD_REQ_PROC;
352
 
353
  -- this process generates the read acknowledge 1 clock after read enable
354
  -- is presented to the BRAM block. The BRAM block has a 1 clock delay
355
  -- from read enable to data out.
356
  BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
357
  begin
358
 
359
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
360
      if ( Bus2IP_Reset = '1' ) then
361
        mem_read_ack_dly1 <= '0';
362
      else
363
        mem_read_ack_dly1 <= mem_read_req;
364
      end if;
365
    end if;
366
 
367
  end process BRAM_RD_ACK_PROC;
368
 
369
    -- address logic
370
  Sel_MNO <= mem_select(0);
371
  with mem_select(1 to 4) select
372
    Sel_Op <= "00" when "1000",
373
                   "01" when "0100",
374
                                  "10" when "0010",
375
                                  "11" when others;
376
 
377
 
378
  core_rw_address <= Sel_MNO & Sel_Op & mem_address;
379
 
380
  -- data-in
381
  core_data_in <= Bus2IP_Data;
382
  core_fifo_din <= Bus2IP_Data;
383
  core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
384
  core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
385
  -- no read mux required, we can only read from core_data_out
386
  mem_ip2bus_data <= core_data_out;
387
 
388
  ------------------------------------------
389
  -- Map slv_reg0 bits to core control signals 
390
  ------------------------------------------
391 65 JonasDC
 
392 2 JonasDC
  core_p_sel <= slv_reg0(0 to 1);
393
  core_dest_op_single <= slv_reg0(2 to 3);
394
  core_x_sel_single <= slv_reg0(4 to 5);
395
  core_y_sel_single <= slv_reg0(6 to 7);
396 65 JonasDC
  core_start <= slv_reg0(8);
397
  core_exp_m <= slv_reg0(9);
398 77 JonasDC
  core_modulus_sel <= slv_reg0(10);
399 2 JonasDC
 
400
  ------------------------------------------
401
  -- Multiplier core instance
402
  ------------------------------------------
403 40 JonasDC
  the_multiplier: mod_sim_exp_core
404 43 JonasDC
  generic map(
405
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
406
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
407
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
408 65 JonasDC
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
409 73 JonasDC
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
410
    C_MEM_STYLE       => C_MEM_STYLE,
411 84 JonasDC
    C_FPGA_MAN        => C_FPGA_MAN
412 43 JonasDC
  )
413
  port map(
414
    clk   => Bus2IP_Clk,
415
    reset => Bus2IP_Reset,
416
      -- operand memory interface (plb shared memory)
417
    write_enable => core_write_enable,
418
    data_in      => core_data_in,
419
    rw_address   => core_rw_address,
420
    data_out     => core_data_out,
421
    collision    => core_mem_collision,
422
      -- op_sel fifo interface
423
    fifo_din    => core_fifo_din,
424
    fifo_push   => core_fifo_push,
425
    fifo_full   => core_fifo_full,
426
    fifo_nopush => core_fifo_nopush,
427
      -- ctrl signals
428
    start          => core_start,
429 45 JonasDC
    exp_m          => core_exp_m,
430 43 JonasDC
    ready          => core_ready,
431
    x_sel_single   => core_x_sel_single,
432
    y_sel_single   => core_y_sel_single,
433
    dest_op_single => core_dest_op_single,
434
    p_sel          => core_p_sel,
435 65 JonasDC
    calc_time      => calc_time,
436
    modulus_sel    => core_modulus_sel
437 2 JonasDC
  );
438
 
439 43 JonasDC
 
440 2 JonasDC
  ------------------------------------------
441
  -- Drive IP to Bus signals
442
  ------------------------------------------
443
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
444
                  mem_ip2bus_data when mem_read_ack = '1' else
445
                  (others => '0');
446
 
447
  IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
448
  IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
449
  IP2Bus_Error <= '0';
450
 
451
end IMP;

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