OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_asym.vhd] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 66 JonasDC
----------------------------------------------------------------------  
2
----  tdpram_asym                                                 ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    behavorial description of an asymmetric true dual port    ----
10
----    ram with one (widthA)-bit read/write port and one 32-bit  ----
11
----    read/write port. Made using the templates of xilinx and   ----
12
----    altera for asymmetric ram.                                ----
13
----                                                              ---- 
14
----  Dependencies: none                                          ----
15
----                                                              ----
16
----  Authors:                                                    ----
17
----      - Geoffrey Ottoy, DraMCo research group                 ----
18
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
19
----                                                              ---- 
20
---------------------------------------------------------------------- 
21
----                                                              ---- 
22
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
23
----                                                              ---- 
24
---- This source file may be used and distributed without         ---- 
25
---- restriction provided that this copyright statement is not    ---- 
26
---- removed from the file and that any derivative work contains  ---- 
27
---- the original copyright notice and the associated disclaimer. ---- 
28
----                                                              ---- 
29
---- This source file is free software; you can redistribute it   ---- 
30
---- and/or modify it under the terms of the GNU Lesser General   ---- 
31
---- Public License as published by the Free Software Foundation; ---- 
32
---- either version 2.1 of the License, or (at your option) any   ---- 
33
---- later version.                                               ---- 
34
----                                                              ---- 
35
---- This source is distributed in the hope that it will be       ---- 
36
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
37
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
38
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
39
---- details.                                                     ---- 
40
----                                                              ---- 
41
---- You should have received a copy of the GNU Lesser General    ---- 
42
---- Public License along with this source; if not, download it   ---- 
43
---- from http://www.opencores.org/lgpl.shtml                     ---- 
44
----                                                              ---- 
45
----------------------------------------------------------------------
46
 
47
library ieee;
48
use ieee.std_logic_1164.all;
49
use ieee.std_logic_unsigned.all;
50
use ieee.std_logic_arith.all;
51
 
52
library mod_sim_exp;
53
use mod_sim_exp.std_functions.all;
54
 
55
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition 
56
-- option on or contstraint below on) and widthA 1,2,4,8,16
57
-- xilinx infers ramblocks from a depth of 2 and widthA 1,2,4,8,16,32
58
entity tdpram_asym is
59
  generic (
60
    depthB : integer := 4; -- nr of 32-bit words
61
    widthA : integer := 2;  -- port A width, must be smaller than or equal to 32
62
    device : string  := "xilinx"
63
  );
64
  port  (
65
    clk : in std_logic;
66
    -- port A (widthA)-bit
67
    addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
68
    weA   : in std_logic;
69
    dinA  : in std_logic_vector(widthA-1 downto 0);
70
    doutA : out std_logic_vector(widthA-1 downto 0);
71
    -- port B 32-bit
72
    addrB : in std_logic_vector(log2(depthB)-1 downto 0);
73
    weB   : in std_logic;
74
    dinB  : in std_logic_vector(31 downto 0);
75
    doutB : out std_logic_vector(31 downto 0)
76
  );
77
end tdpram_asym;
78
 
79
architecture behavorial of tdpram_asym is
80
  -- constants
81
  constant R : natural := 32/widthA; -- ratio
82
begin
83
 
84
  xilinx_device : if device="xilinx" generate
85
    -- An asymmetric RAM is modelled in a similar way as a symmetric RAM, with an
86
    -- array of array object. Its aspect ratio corresponds to the port with the
87
    -- lower data width (larger depth)
88
    type ramType is array (0 to ((depthB*32)/widthA)-1) of std_logic_vector(widthA-1 downto 0);
89
 
90
    -- You need to declare ram as a shared variable when :
91
    --   - the RAM has two write ports,
92
    --   - the RAM has only one write port whose data width is maxWIDTH
93
    -- In all other cases, ram can be a signal.
94
    shared variable ram : ramType := (others => (others => '0'));
95
         signal clkA : std_logic;
96
         signal clkB : std_logic;
97
 
98
  begin
99
         clkA <= clk;
100
    process (clkA)
101
    begin
102
      if rising_edge(clkA) then
103
        if weA = '1' then
104
          ram(conv_integer(addrA)) := dinA;
105
        end if;
106
        doutA <= ram(conv_integer(addrA));
107
      end if;
108
    end process;
109
 
110
         clkB <= clk;
111
    process (clkB)
112
    begin
113
      if rising_edge(clkB) then
114
        for i in 0 to R-1 loop
115
          if weB = '1' then
116
            ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))))
117
              := dinB((i+1)*widthA-1 downto i*widthA);
118
          end if;
119
          doutB((i+1)*widthA-1 downto i*widthA)
120
            <= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))));
121
        end loop;
122
      end if;
123
    end process;
124
  end generate;
125
 
126
  altera_device : if device="altera" generate
127
    -- Use a multidimensional array to model mixed-width 
128
    type word_t is array(R-1 downto 0) of std_logic_vector(widthA-1 downto 0);
129
    type ram_t is array (0 to depthB-1) of word_t;
130
 
131
    -- altera constraints:
132
    -- for smal depths:
133
    --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
134
    --  may be left commented.
135
    --  uncomment this attribute if that option is off and you know wich primitives should be used.
136
    --attribute ramstyle : string;
137
    --attribute ramstyle of RAM : signal is "M9K, no_rw_check";
138
 
139
    -- delcare the RAM
140
    signal ram : ram_t;
141
    signal wB_local : word_t;
142
    signal qB_local : word_t;
143
 
144
  begin  -- rtl
145
    -- Re-organize the write data to match the RAM word type
146
    unpack: for i in 0 to R-1 generate
147
      wB_local(i) <= dinB(widthA*(i+1)-1 downto widthA*i);
148
      doutB(widthA*(i+1)-1 downto widthA*i) <= qB_local(i);
149
    end generate unpack;
150
 
151
    --port B
152
    process(clk)
153
    begin
154
      if(rising_edge(clk)) then
155
        if(weB = '1') then
156
          ram(conv_integer(addrB)) <= wB_local;
157
        end if;
158
        qB_local <= ram(conv_integer(addrB));
159
      end if;
160
    end process;
161
 
162
    -- port A
163
    process(clk)
164
    begin
165
      if(rising_edge(clk)) then
166
        doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
167
        if(weA ='1') then
168
          ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
169
        end if;
170
      end if;
171
    end process;
172
  end generate;
173
 
174
end behavorial;
175
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.