OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpramblock_asym.vhd] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 66 JonasDC
----------------------------------------------------------------------  
2
----  tdpramblock_asym                                            ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    structural description of an asymmetric true dual port    ----
10
----    ram with one 32-bit read/write port and one (width)-bit   ----
11
----    read/write port.                                          ----
12
----                                                              ---- 
13
----  Dependencies: tdpram_asym                                   ----
14
----                                                              ----
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
use ieee.std_logic_arith.all;
50
 
51
library mod_sim_exp;
52
use mod_sim_exp.std_functions.all;
53
 
54
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition option on)
55
--    and width 64,128,256,512
56
-- xilinx infers ramblocks from a depth of 2 and width 32,64,128,256,512
57
entity tdpramblock_asym is
58
  generic (
59
    depth  : integer := 4;    -- nr of (width)-bit words
60
    width  : integer := 512;  -- width of portB
61
    device : string  := "xilinx"
62
  );
63
  port  (
64
    clk : in std_logic;
65
    -- port A 32-bit
66
    addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
67
    weA   : in std_logic;
68
    dinA  : in std_logic_vector(31 downto 0);
69
    doutA : out std_logic_vector(31 downto 0);
70
    -- port B (width)-bit
71
    addrB : in std_logic_vector(log2(depth)-1 downto 0);
72
    weB   : in std_logic;
73
    dinB  : in std_logic_vector(width-1 downto 0);
74
    doutB : out std_logic_vector(width-1 downto 0)
75
  );
76
end tdpramblock_asym;
77
 
78
architecture structural of tdpramblock_asym is
79
   -- constants
80
   constant nrRAMs    : integer := width/32;
81
   constant RAMwidthA : integer := 32/nrRAMs;
82
 
83
   -- interconnection signals
84
   type word_array is array (nrRAMs-1 downto 0) of std_logic_vector(31 downto 0);
85
   signal doutB_RAM : word_array;
86
   signal dinB_RAM  : word_array;
87
 begin
88
 
89
  ramblocks : for i in 0 to nrRAMs-1 generate
90
    ramblock : entity mod_sim_exp.tdpram_asym
91
    generic map(
92
      widthA => RAMwidthA,
93
      depthB => depth,
94
      device => device
95
    )
96
    port map(
97
      clk => clk,
98
      -- port A (widthA)-bit
99
      addrA => addrA,
100
      weA   => weA,
101
      dinA  => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
102
      doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
103
      -- port B 32-bit
104
      addrB => addrB,
105
      weB   => weB,
106
      dinB  => dinB_RAM(i),
107
      doutB => doutB_RAM(i)
108
    );
109
 
110
    map_ioB : for j in 0 to nrRAMs-1 generate
111
      -- output
112
      doutB(j*32+(i+1)*RAMwidthA-1 downto j*32+i*RAMwidthA)
113
          <= doutB_RAM(i)((j+1)*RAMwidthA-1 downto j*RAMwidthA);
114
      -- input
115
      dinB_RAM(i)((j+1)*RAMwidthA-1 downto j*RAMwidthA)
116
          <= dinB(j*32+(i+1)*RAMwidthA-1 downto j*32+i*RAMwidthA);
117
    end generate;
118
  end generate;
119
 
120
end structural;
121
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.