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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpramblock_asym.vhd] - Blame information for rev 94

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1 66 JonasDC
----------------------------------------------------------------------  
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----  tdpramblock_asym                                            ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    structural description of an asymmetric true dual port    ----
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----    ram with one 32-bit read/write port and one (width)-bit   ----
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----    read/write port.                                          ----
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----                                                              ---- 
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----  Dependencies: tdpram_asym                                   ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library mod_sim_exp;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition option on)
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--    and width 64,128,256,512
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-- xilinx infers ramblocks from a depth of 2 and width 32,64,128,256,512
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entity tdpramblock_asym is
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  generic (
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    depth  : integer := 4;    -- nr of (width)-bit words
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    width  : integer := 512;  -- width of portB
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    device : string  := "xilinx"
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  );
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  port (
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    -- port A 32-bit
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    clkA  : in std_logic;
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    addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
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    weA   : in std_logic;
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    dinA  : in std_logic_vector(31 downto 0);
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    doutA : out std_logic_vector(31 downto 0);
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    -- port B (width)-bit
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    clkB  : in std_logic;
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    addrB : in std_logic_vector(log2(depth)-1 downto 0);
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    weB   : in std_logic;
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    dinB  : in std_logic_vector(width-1 downto 0);
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    doutB : out std_logic_vector(width-1 downto 0)
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  );
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end tdpramblock_asym;
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architecture structural of tdpramblock_asym is
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   -- constants
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   constant nrRAMs    : integer := width/32;
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   constant RAMwidthA : integer := 32/nrRAMs;
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   -- interconnection signals
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   type word_array is array (nrRAMs-1 downto 0) of std_logic_vector(31 downto 0);
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   signal doutB_RAM : word_array;
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   signal dinB_RAM  : word_array;
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 begin
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  ramblocks : for i in 0 to nrRAMs-1 generate
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    ramblock : tdpram_asym
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    generic map(
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      widthA => RAMwidthA,
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      depthB => depth,
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      device => device
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    )
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    port map(
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      -- port A (widthA)-bit
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      clkA  => clkA,
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      addrA => addrA,
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      weA   => weA,
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      dinA  => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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      doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
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      -- port B 32-bit
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      clkB  => clkB,
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      addrB => addrB,
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      weB   => weB,
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      dinB  => dinB_RAM(i),
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      doutB => doutB_RAM(i)
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    );
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    map_ioB : for j in 0 to nrRAMs-1 generate
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      -- output
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      doutB(j*32+(i+1)*RAMwidthA-1 downto j*32+i*RAMwidthA)
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          <= doutB_RAM(i)((j+1)*RAMwidthA-1 downto j*RAMwidthA);
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      -- input
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      dinB_RAM(i)((j+1)*RAMwidthA-1 downto j*RAMwidthA)
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          <= dinB(j*32+(i+1)*RAMwidthA-1 downto j*32+i*RAMwidthA);
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    end generate;
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  end generate;
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end structural;
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