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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Blame information for rev 65

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Line No. Rev Author Line
1 3 JonasDC
#VCOM    = /usr/local/bin/vcom
2 65 JonasDC
VCOMOPS = -explicit -check_synthesis -2002 -quiet
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VLOGOPS = -vopt -nocovercells
4 3 JonasDC
#MAKEFLAGS = --silent
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HDL_DIR = ../rtl/vhdl/
6 65 JonasDC
VER_DIR = ../rtl/verilog/
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8
 
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##
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# avs_aes hdl files
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##
12 65 JonasDC
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
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                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
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                 $(HDL_DIR)/ram/dpram_generic.vhd \
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                 $(HDL_DIR)/ram/tdpram_generic.vhd \
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                 $(HDL_DIR)/core/fifo_generic.vhd \
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                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
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                 $(HDL_DIR)/core/operand_ram_gen.vhd \
19 3 JonasDC
                 $(HDL_DIR)/core/adder_block.vhd \
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                 $(HDL_DIR)/core/autorun_cntrl.vhd \
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                 $(HDL_DIR)/core/cell_1b_adder.vhd \
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                 $(HDL_DIR)/core/cell_1b_mux.vhd \
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                 $(HDL_DIR)/core/cell_1b.vhd \
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                 $(HDL_DIR)/core/counter_sync.vhd \
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                 $(HDL_DIR)/core/d_flip_flop.vhd \
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                 $(HDL_DIR)/core/fifo_primitive.vhd \
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                 $(HDL_DIR)/core/modulus_ram.vhd \
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                 $(HDL_DIR)/core/mont_ctrl.vhd \
29 24 JonasDC
                 $(HDL_DIR)/core/mod_sim_exp_core.vhd \
30 3 JonasDC
                 $(HDL_DIR)/core/operand_dp.vhd \
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                 $(HDL_DIR)/core/operand_mem.vhd \
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                 $(HDL_DIR)/core/operand_ram.vhd \
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                 $(HDL_DIR)/core/operands_sp.vhd \
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                 $(HDL_DIR)/core/register_1b.vhd \
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                 $(HDL_DIR)/core/register_n.vhd \
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                 $(HDL_DIR)/core/standard_cell_block.vhd \
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                 $(HDL_DIR)/core/stepping_logic.vhd \
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                 $(HDL_DIR)/core/x_shift_reg.vhd \
39 28 JonasDC
                 $(HDL_DIR)/core/sys_stage.vhd \
40 30 JonasDC
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
41 31 JonasDC
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
42 28 JonasDC
                 $(HDL_DIR)/core/sys_pipeline.vhd \
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                 $(HDL_DIR)/core/mont_multiplier.vhd \
44 3 JonasDC
 
45 65 JonasDC
VER_SRC =$(VER_DIR)generic_spram.v \
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                $(VER_DIR)generic_dpram.v \
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                $(VER_DIR)generic_tpram.v \
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                $(VER_DIR)generic_fifo_sc_a.v \
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                $(VER_DIR)generic_fifo_sc_b.v \
50 3 JonasDC
 
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##
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# Testbench HDL file
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##
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TB_SRC_DIR = ../bench/vhdl/
55 24 JonasDC
TB_SRC =  $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
56 3 JonasDC
 
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#######################################
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all: mod_sim_exp
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clean:
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        rm -rf *_lib
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mod_sim_exp_lib:
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        vlib mod_sim_exp
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work_lib:
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        vlib work
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libs: mod_sim_exp work_lib
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mod_sim_exp_com: mod_sim_exp_lib
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        #echo --
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        #echo building Modular Exponentiation Core
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        #echo --
75 65 JonasDC
        #vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
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        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
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        #echo Done!
78 3 JonasDC
 
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mod_sim_exp_tb: work_lib
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        #echo --
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        #echo building Modular Exponentiation Core Testbench
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        #echo --
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        vcom $(VCOMOPS) -work work $(TB_SRC)
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mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
86 24 JonasDC
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb

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