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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Blame information for rev 84

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Line No. Rev Author Line
1 3 JonasDC
#VCOM    = /usr/local/bin/vcom
2 65 JonasDC
VCOMOPS = -explicit -check_synthesis -2002 -quiet
3 3 JonasDC
#MAKEFLAGS = --silent
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HDL_DIR = ../rtl/vhdl/
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##
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# avs_aes hdl files
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##
9 84 JonasDC
CORE_SRC =$(HDL_DIR)core/std_functions.vhd \
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                 $(HDL_DIR)core/mod_sim_exp_pkg.vhd \
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                 $(HDL_DIR)ram/dpram_generic.vhd \
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                 $(HDL_DIR)ram/tdpram_generic.vhd \
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                 $(HDL_DIR)ram/dpram_asym.vhd \
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                 $(HDL_DIR)ram/dpramblock_asym.vhd \
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                 $(HDL_DIR)core/modulus_ram_asym.vhd \
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                 $(HDL_DIR)ram/tdpram_asym.vhd \
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                 $(HDL_DIR)ram/tdpramblock_asym.vhd \
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                 $(HDL_DIR)core/operand_ram_asym.vhd \
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                 $(HDL_DIR)core/fifo_generic.vhd \
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                 $(HDL_DIR)core/modulus_ram_gen.vhd \
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                 $(HDL_DIR)core/operand_ram_gen.vhd \
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                 $(HDL_DIR)core/adder_block.vhd \
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                 $(HDL_DIR)core/autorun_cntrl.vhd \
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                 $(HDL_DIR)core/cell_1b_adder.vhd \
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                 $(HDL_DIR)core/cell_1b_mux.vhd \
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                 $(HDL_DIR)core/cell_1b.vhd \
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                 $(HDL_DIR)core/counter_sync.vhd \
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                 $(HDL_DIR)core/d_flip_flop.vhd \
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                 $(HDL_DIR)core/fifo_primitive.vhd \
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                 $(HDL_DIR)core/modulus_ram.vhd \
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                 $(HDL_DIR)core/mont_ctrl.vhd \
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                 $(HDL_DIR)core/mod_sim_exp_core.vhd \
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                 $(HDL_DIR)core/operand_dp.vhd \
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                 $(HDL_DIR)core/operand_mem.vhd \
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                 $(HDL_DIR)core/operand_ram.vhd \
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                 $(HDL_DIR)core/operands_sp.vhd \
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                 $(HDL_DIR)core/register_1b.vhd \
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                 $(HDL_DIR)core/register_n.vhd \
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                 $(HDL_DIR)core/standard_cell_block.vhd \
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                 $(HDL_DIR)core/stepping_logic.vhd \
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                 $(HDL_DIR)core/x_shift_reg.vhd \
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                 $(HDL_DIR)core/sys_stage.vhd \
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                 $(HDL_DIR)core/sys_last_cell_logic.vhd \
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                 $(HDL_DIR)core/sys_first_cell_logic.vhd \
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                 $(HDL_DIR)core/sys_pipeline.vhd \
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                 $(HDL_DIR)core/mont_multiplier.vhd \
47 3 JonasDC
 
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##
50 84 JonasDC
# Testbench HDL files
51 3 JonasDC
##
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TB_SRC_DIR = ../bench/vhdl/
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TB_SRC =        $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \
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                        $(TB_SRC_DIR)msec_axi_tb.vhd
55 3 JonasDC
 
56 84 JonasDC
##
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# Interface HDL files
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##
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IF_SRC_DIR = ../rtl/vhdl/interface/
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IF_SRC =        $(IF_SRC_DIR)axi/msec_ipcore_axilite.vhd
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62 3 JonasDC
#######################################
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all: mod_sim_exp
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clean:
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        rm -rf *_lib
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mod_sim_exp_lib:
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        vlib mod_sim_exp
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work_lib:
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        vlib work
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74 84 JonasDC
libs: mod_sim_exp_lib work_lib
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mod_sim_exp_com: mod_sim_exp_lib
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        #echo --
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        #echo building Modular Exponentiation Core
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        #echo --
80 65 JonasDC
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
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        #echo Done!
82 3 JonasDC
 
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mod_sim_exp_tb: work_lib
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        #echo --
85 84 JonasDC
        #echo building Modular Exponentiation Core Testbenches
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        #echo --
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        vcom $(VCOMOPS) -work work $(TB_SRC)
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89 84 JonasDC
msec_if: work_lib
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        #echo --
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        #echo building Modular Exponentiation Core Interface
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        #echo --
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        vcom $(VCOMOPS) -work work $(IF_SRC)
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95 3 JonasDC
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
96 24 JonasDC
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
97 84 JonasDC
 
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mod_sim_exp_axi: mod_sim_exp_com msec_if mod_sim_exp_tb
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        vsim -c -do mod_sim_exp.do -lib work msec_axi_tb

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