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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [fifo_size.v] - Blame information for rev 2

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/*
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 * fifo_size.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * fifo_size.v
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 *
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 * Dimensioning of various fifos. Tuning parameters; handle with care.
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 *
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 * Summary:
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 *
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 * motcomp  throttles motcomp_addr_gen (via fifos_almost_full) when dst_wr_almost_full || fwd_wr_addr_almost_full || bwd_wr_addr_almost_full .
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 * This is tuneable via ADDR_THRESHOLD.
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 * ADDR_THRESHOLD has to be big enough to allow motcomp_addr_gen to generate all memory requests for a complete macroblock.
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 *
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 * framestore_request stops handling requests from fwd motion compensation when fwd_wr_dta_almost_full
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 * framestore_request stops handling requests from bwd motion compensation when bwd_wr_dta_almost_full
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 * framestore_request stops handling requests from display when disp_wr_dta_almost_full
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 * framestore_request stops handling requests for circular video buffer reads when vbr_wr_almost_full
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 * This is tuneable via DTA_THRESHOLD.
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 * If memory latency is high, DTA_THRESHOLD should be high as well.
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 *
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 * framestore_request stops handling requests when mem_req fills up (mem_req_wr_almost_full).
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 * This is tuneable via MEM_THRESHOLD.
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 *
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 * memory controller mem_ctl stops handling requests when memory results fifo almost full (mem_res_wr_almost_full).
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 * This is tuneable via MEM_THRESHOLD.
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 *
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 * framestore_response stops draining memory results fifo mem_res when fwd_wr_dta_full, bwd_wr_dta_full, disp_wr_dta_full or vbr_wr_full.
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 *
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 * mem_tag fifo size is smaller than mem_req or mem_res; hence the number of
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 * memory requests "in flight" - including memory latency - is at most mem_tag fifo size.
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 * This allows one to dimension DTA_THRESHOLD: if DTA_THRESHOLD is smaller
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 * than mem_tag fifo size, you run the risk of overflowing a data fifo.
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 * Indeed, framestore_request will stop issuing read requests when the data fifo has
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 * less than DTA_THRESHOLD space left; but since there may be up to mem_tag
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 * fifo size (= 2**MEMTAG_DEPTH) requests already queued for execution,
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 * the pending requests may overflow the data fifo if DTA_THRESHOLD < 2**MEMTAG_DEPTH.
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 * Hence always choose DTA_THRESHOLD > 2**MEMTAG_DEPTH.
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 *
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 * Remark: fifo sizes in this file are influenced by dual-port ram sizes available in FPGA's, typically 18 or 36 kbit.
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 * As such, fifo sizes in this file tend not to be minimal fifo sizes.
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 */
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/*
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 * dct_coeff fifo. 31 bits wide.
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 * Run/Length Values fifo from vld. Input for rld.
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 */
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parameter
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  RLD_DEPTH          = 9'd7, // one 4:2:0 macroblock = 6 blocks at 64 run/length values per block maximum = 384 entries maximum
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  RLD_THRESHOLD      = 9'd2,
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/*
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 * predict_err_fifo. 72 bits wide.
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 * Inverse Discrete Cosine Transform Output. Contains prediction error.
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 */
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  PREDICT_DEPTH      = 9'd8,
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  PREDICT_THRESHOLD  = 9'd64, // big enough so 1 macroblock ( 6 blocks @ 8 rows each ) fits.
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/*
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 * mvec fifo. 206 bits wide.
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 * prediction motion vector fifo from vld. Input for motvec.
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 */
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  MVEC_DEPTH          = 9'd3,
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  MVEC_THRESHOLD      = 9'd2,
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/*
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 *
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 */
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  ADDR_DEPTH      = 9'd8,
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  ADDR_THRESHOLD  = 9'd8,
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  DTA_DEPTH       = 9'd8,
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  DTA_THRESHOLD   = 9'd64,
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  MOTCOMP_ADDR_THRESHOLD  = 9'd144, /* enough for motcomp_addrgen to produce all reads necessary to process a complete macroblock
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                                       number of addresses produced by motcomp_addrgen = no. of lumi blocks * lumi_rows * columns + no. of chromi blocks * max. chromi rows * colums = 4 * 9 * 2 + 2 * 10 * 2 = 112 (see motcomp_addrgen)
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                                       number of addresses in the mem_addr pipe: 13 (13 tages, numbered 0 to 12)
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                                       together: 112 + 13 = 125.
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                                       144: safety margin, just in case.
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                                       */
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/*
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 * Circular Video Buffer. vbuf_write_fifo and vbuf_read_fifo are both 64 bits wide.
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 * from stream input to getbits.
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 */
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  VBUF_WR_DEPTH      = DTA_DEPTH,
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  VBUF_WR_THRESHOLD  = 9'd128,
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  VBUF_RD_DEPTH      = DTA_DEPTH,
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  VBUF_RD_THRESHOLD  = 9'd32,
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/*
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 * fwd_reader. addr fifo is 22 bits wide; data fifo is 64 bits wide.
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 * Reads the data for forward motion compensation.
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 * Two fifo's: one sending addresses to be read to the frame store;
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 * one receiving data read from the frame store.
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 */
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  FWD_ADDR_DEPTH     = ADDR_DEPTH,
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  FWD_ADDR_THRESHOLD = MOTCOMP_ADDR_THRESHOLD,
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  FWD_DTA_DEPTH      = DTA_DEPTH,
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  FWD_DTA_THRESHOLD  = DTA_THRESHOLD, // less than half of dta fifo size
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/*
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 * bwd_reader. addr fifo is 22 bits wide; data fifo is 64 bits wide.
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 * Reads the data for backward motion compensation.
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 * Two fifo's: one sending addresses to be read to the frame store;
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 * one receiving data read from the frame store.
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 */
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  BWD_ADDR_DEPTH     = ADDR_DEPTH,
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  BWD_ADDR_THRESHOLD = MOTCOMP_ADDR_THRESHOLD,
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  BWD_DTA_DEPTH      = DTA_DEPTH,
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  BWD_DTA_THRESHOLD  = DTA_THRESHOLD,
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/*
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 * dst_fifo. 35 bits wide.
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 * Motion compensation. Queues the addresses where the reconstructed pixels need to be written
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 * until prediction error, forward and backward motion compensation data are available.
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 */
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  DST_DEPTH          = ADDR_DEPTH,
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  DST_THRESHOLD      = MOTCOMP_ADDR_THRESHOLD,
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/*
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 * recon_writer. 86 bits wide.
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 * Motion compensation. Writes reconstructed pixels to the frame store.
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 */
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  RECON_DEPTH        = DTA_DEPTH,
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  RECON_THRESHOLD    = DTA_THRESHOLD,
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/*
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 * disp_reader. addr fifo is 22 bits wide; data fifo is 64 bits wide.
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 * Reads pixels from the frame store for displaying.
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 * Two fifo's: one sending addresses to be read to the frame store;
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 * one receiving data read from the frame store.
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 */
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  DISP_ADDR_DEPTH    = ADDR_DEPTH,
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  DISP_ADDR_THRESHOLD= 9'd32,         // about 8 times RESAMPLE_THRESHOLD
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  DISP_DTA_DEPTH     = DTA_DEPTH,     // disp_reader data fifo should never be empty
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  DISP_DTA_THRESHOLD = DTA_THRESHOLD, // less than half of dta fifo size.
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/*
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 * resample_fifo. 3 bits wide.
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 * Chroma resampling. Fifo from resample_addr to resample_dta.
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 */
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  RESAMPLE_DEPTH     = 9'd8,
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  RESAMPLE_THRESHOLD = 9'd4,
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/*
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 * pixel_fifo. 35 bits wide.
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 * From the decoding process to the display process
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 */
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  PIXEL_DEPTH        = 9'd10,
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  PIXEL_THRESHOLD    = 9'd32,
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/*
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 * osd_writer. 86 bits wide.
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 * On-Screen Display. Writes on-screen display to the frame store.
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 */
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  OSD_DEPTH          = 9'd5,
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  OSD_THRESHOLD      = 9'd8,
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/*
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 * threshold to make framestore_request stop writing before mem_request_fifo, mem_tag_fifo or mem_response_fifo overflow.
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 */
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  MEM_THRESHOLD      = 9'd16,
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/*
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 * mem_request_fifo. 88 bits wide.
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 * Memory subsystem. Sends read, write and refresh commands to the memory controller.
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 */
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  MEMREQ_DEPTH      = 9'd6,
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  MEMREQ_THRESHOLD  = MEM_THRESHOLD,
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/*
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 * mem_tag_fifo. 3 bits wide.
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 * Memory subsystem. Queues tags of read commands sent to the memory controller.
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 */
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  MEMTAG_DEPTH      = 9'd5,
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  MEMTAG_THRESHOLD  = MEM_THRESHOLD,
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/*
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 * mem_response_fifo. 64 bits wide.
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 * Memory subsystem. Receives data read from the memory controller.
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 */
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  MEMRESP_DEPTH     = 9'd7,
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  MEMRESP_THRESHOLD = 9'd64;
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/* not truncated */

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